| SCORE | LINE | TOGGLE | BRANCH |
| 65.30 | 65.30 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.54 | 100.00 | 70.63 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_7__3_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.80 | 100.00 | 68.40 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.26 | 100.00 | 69.79 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.36 | 100.00 | 70.09 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.38 | 100.00 | 70.15 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.18 | 100.00 | 69.55 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.38 | 100.00 | 70.14 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.37 | 100.00 | 70.12 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.36 | 100.00 | 70.07 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 85.85 | 85.85 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 87.67 | 87.67 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 64.71 | 64.71 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 86.79 | 86.79 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 82.08 | 82.08 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 85.85 | 85.85 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 84.91 | 84.91 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 88.36 | 88.36 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.17 | 65.17 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.53 | 100.00 | 70.60 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_7__4_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.44 | 100.00 | 70.32 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.26 | 100.00 | 69.79 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.01 | 100.00 | 69.04 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.42 | 100.00 | 70.25 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.52 | 100.00 | 70.56 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.94 | 100.00 | 68.81 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.37 | 100.00 | 70.10 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.17 | 100.00 | 69.50 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.18 | 100.00 | 69.53 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 88.36 | 88.36 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 83.02 | 83.02 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 85.85 | 85.85 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 85.85 | 85.85 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 86.99 | 86.99 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 86.79 | 86.79 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 82.08 | 82.08 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 86.79 | 86.79 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 82.08 | 82.08 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.15 | 65.15 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.52 | 100.00 | 70.56 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_7__5_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.32 | 100.00 | 69.96 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.39 | 100.00 | 70.17 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.46 | 100.00 | 70.37 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.16 | 100.00 | 69.48 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.31 | 100.00 | 69.94 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.17 | 100.00 | 69.52 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.31 | 100.00 | 69.94 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.13 | 100.00 | 69.40 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 87.67 | 87.67 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 83.96 | 83.96 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 82.08 | 82.08 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 83.02 | 83.02 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 87.67 | 87.67 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 86.99 | 86.99 | ||
| mux_fle_9_in_1 | 88.36 | 88.36 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.10 | 65.10 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.47 | 100.00 | 70.40 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_7__6_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.12 | 100.00 | 69.35 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.22 | 100.00 | 69.66 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.36 | 100.00 | 70.07 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.02 | 100.00 | 69.07 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.04 | 100.00 | 69.12 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.14 | 100.00 | 69.42 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.16 | 100.00 | 69.47 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 86.99 | 86.99 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 88.36 | 88.36 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 82.08 | 82.08 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.84 | 64.84 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.35 | 100.00 | 70.06 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_7__7_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.93 | 100.00 | 68.80 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.96 | 100.00 | 68.88 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.26 | 100.00 | 69.79 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.83 | 100.00 | 68.48 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.96 | 100.00 | 68.89 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.18 | 100.00 | 69.53 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.16 | 100.00 | 69.48 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 88.36 | 88.36 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 61.76 | 61.76 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 81.13 | 81.13 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 85.85 | 85.85 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 87.67 | 87.67 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.58 | 64.58 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.22 | 100.00 | 69.65 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.64 | 80.64 | grid_clb_7__8_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 0.00 | 0.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 0.00 | 0.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 0.00 | 0.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 0.00 | 0.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 0.00 | 0.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 0.00 | 0.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 0.00 | 0.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 0.00 | 0.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 0.00 | 0.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 0.00 | 0.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 0.00 | 0.00 | ||
| logical_tile_clb_mode_default__fle_0 | 82.82 | 100.00 | 68.47 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.87 | 100.00 | 68.61 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.63 | 100.00 | 67.88 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.81 | 100.00 | 68.43 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.66 | 100.00 | 67.99 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.88 | 100.00 | 68.63 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.92 | 100.00 | 68.75 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.08 | 100.00 | 69.24 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 45.45 | 45.45 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 85.85 | 85.85 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 87.67 | 87.67 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 83.02 | 83.02 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 88.36 | 88.36 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 83.02 | 83.02 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 83.96 | 83.96 | ||
| mux_fle_6_in_5 | 83.02 | 83.02 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 87.67 | 87.67 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.79 | 64.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.36 | 100.00 | 70.09 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_7__9_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.77 | 100.00 | 68.30 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.89 | 100.00 | 68.66 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.33 | 100.00 | 69.99 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.22 | 100.00 | 69.66 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.20 | 100.00 | 69.60 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.88 | 100.00 | 68.65 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.08 | 100.00 | 69.24 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.10 | 100.00 | 69.30 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 82.08 | 82.08 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 83.96 | 83.96 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 87.67 | 87.67 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 87.67 | 87.67 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 82.08 | 82.08 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 77.36 | 77.36 | ||
| mux_fle_4_clk_0 | 64.71 | 64.71 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 86.99 | 86.99 | ||
| mux_fle_4_in_3 | 83.02 | 83.02 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 64.71 | 64.71 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 81.13 | 81.13 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 88.36 | 88.36 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 86.79 | 86.79 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 83.96 | 83.96 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.29 | 65.29 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.54 | 100.00 | 70.62 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_7__10_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.86 | 100.00 | 68.57 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.49 | 100.00 | 70.46 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.51 | 100.00 | 70.53 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.19 | 100.00 | 69.58 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.19 | 100.00 | 69.56 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.43 | 100.00 | 70.28 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.20 | 100.00 | 69.60 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.32 | 100.00 | 69.96 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 18.18 | 18.18 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 84.91 | 84.91 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 83.02 | 83.02 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 83.96 | 83.96 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 83.02 | 83.02 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 86.79 | 86.79 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 85.85 | 85.85 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 84.91 | 84.91 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 88.36 | 88.36 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 82.08 | 82.08 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.14 | 65.14 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.36 | 100.00 | 70.08 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.88 | 80.88 | grid_clb_7__11_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.70 | 100.00 | 68.11 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.84 | 100.00 | 68.53 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.16 | 100.00 | 69.48 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.14 | 100.00 | 69.43 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.18 | 100.00 | 69.53 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 45.45 | 45.45 | ||
| mux_fle_0_clk_0 | 61.76 | 61.76 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 79.25 | 79.25 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 87.67 | 87.67 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 83.02 | 83.02 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 83.02 | 83.02 | ||
| mux_fle_2_in_4 | 79.25 | 79.25 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 82.08 | 82.08 | ||
| mux_fle_4_in_4 | 83.02 | 83.02 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 83.02 | 83.02 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 84.91 | 84.91 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 82.08 | 82.08 | ||
| mux_fle_6_in_4 | 83.96 | 83.96 | ||
| mux_fle_6_in_5 | 83.02 | 83.02 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 81.13 | 81.13 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 79.25 | 79.25 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 81.13 | 81.13 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.67 | 64.67 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.27 | 100.00 | 69.82 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.15 | 80.15 | grid_clb_7__12_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.83 | 100.00 | 68.48 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.22 | 100.00 | 69.66 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.88 | 100.00 | 68.63 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.86 | 100.00 | 68.57 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.95 | 100.00 | 68.84 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.20 | 100.00 | 69.60 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.18 | 100.00 | 69.53 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 9.09 | 9.09 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 88.36 | 88.36 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 81.13 | 81.13 | ||
| mux_fle_0_in_4 | 81.13 | 81.13 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 86.99 | 86.99 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 78.30 | 78.30 | ||
| mux_fle_1_in_5 | 82.08 | 82.08 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 87.67 | 87.67 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 87.67 | 87.67 | ||
| mux_fle_3_in_1 | 87.67 | 87.67 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 82.08 | 82.08 | ||
| mux_fle_3_in_5 | 72.64 | 72.64 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 86.30 | 86.30 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 79.25 | 79.25 | ||
| mux_fle_4_in_4 | 81.13 | 81.13 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 87.67 | 87.67 | ||
| mux_fle_5_in_3 | 82.08 | 82.08 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 88.36 | 88.36 | ||
| mux_fle_6_in_3 | 76.42 | 76.42 | ||
| mux_fle_6_in_4 | 83.96 | 83.96 | ||
| mux_fle_6_in_5 | 77.36 | 77.36 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 86.99 | 86.99 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 78.30 | 78.30 | ||
| mux_fle_7_in_4 | 81.13 | 81.13 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 86.99 | 86.99 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 78.30 | 78.30 | ||
| mux_fle_8_in_4 | 79.25 | 79.25 | ||
| mux_fle_8_in_5 | 82.08 | 82.08 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 87.67 | 87.67 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 87.67 | 87.67 | ||
| mux_fle_9_in_3 | 77.36 | 77.36 | ||
| mux_fle_9_in_4 | 78.30 | 78.30 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.00 | 65.00 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.34 | 100.00 | 70.02 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_8__1_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.70 | 100.00 | 68.09 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.17 | 100.00 | 69.52 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.94 | 100.00 | 68.81 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.94 | 100.00 | 68.83 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 78.11 | 100.00 | 54.32 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 61.76 | 61.76 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 81.13 | 81.13 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 82.08 | 82.08 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 81.13 | 81.13 | ||
| mux_fle_1_in_4 | 82.08 | 82.08 | ||
| mux_fle_1_in_5 | 71.70 | 71.70 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 83.02 | 83.02 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 83.02 | 83.02 | ||
| mux_fle_7_clk_0 | 61.76 | 61.76 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.02 | 83.02 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 72.64 | 72.64 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 87.67 | 87.67 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 76.42 | 76.42 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 88.36 | 88.36 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.29 | 65.29 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.51 | 100.00 | 70.54 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_8__2_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.89 | 100.00 | 68.68 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.25 | 100.00 | 69.76 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.04 | 100.00 | 69.11 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.74 | 100.00 | 68.22 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.49 | 100.00 | 70.46 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.17 | 100.00 | 69.50 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.30 | 100.00 | 69.91 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.26 | 100.00 | 69.79 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.40 | 100.00 | 70.20 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.41 | 100.00 | 70.24 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 85.85 | 85.85 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 83.96 | 83.96 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 87.67 | 87.67 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 84.91 | 84.91 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 83.02 | 83.02 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 84.91 | 84.91 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.39 | 65.39 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.51 | 100.00 | 70.54 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_8__3_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.17 | 100.00 | 69.52 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.47 | 100.00 | 70.40 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.01 | 100.00 | 69.02 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.31 | 100.00 | 69.94 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 86.79 | 86.79 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 83.02 | 83.02 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 82.08 | 82.08 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 86.79 | 86.79 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.95 | 64.95 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.51 | 100.00 | 70.52 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_8__4_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.05 | 100.00 | 69.16 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.38 | 100.00 | 70.14 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.36 | 100.00 | 70.09 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.01 | 100.00 | 69.04 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.41 | 100.00 | 70.24 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.23 | 100.00 | 69.68 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.14 | 100.00 | 69.43 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.55 | 100.00 | 70.65 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_4_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 81.13 | 81.13 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 85.85 | 85.85 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 85.85 | 85.85 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 86.99 | 86.99 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 64.71 | 64.71 | ||
| mux_fle_4_in_0 | 86.99 | 86.99 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 86.99 | 86.99 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 82.08 | 82.08 | ||
| mux_fle_7_clk_0 | 61.76 | 61.76 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 88.36 | 88.36 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 82.08 | 82.08 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.44 | 65.44 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.59 | 100.00 | 70.78 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_8__5_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.32 | 100.00 | 69.96 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.32 | 100.00 | 69.96 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.13 | 100.00 | 69.40 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.22 | 100.00 | 69.66 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.08 | 100.00 | 69.24 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.34 | 100.00 | 70.02 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.28 | 100.00 | 69.84 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.23 | 100.00 | 69.68 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.37 | 100.00 | 70.10 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.45 | 100.00 | 70.35 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 84.91 | 84.91 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 86.79 | 86.79 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 80.19 | 80.19 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 87.67 | 87.67 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.94 | 64.94 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.34 | 100.00 | 70.01 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_8__6_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.72 | 100.00 | 68.17 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.78 | 100.00 | 68.34 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.14 | 100.00 | 69.42 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.88 | 100.00 | 68.65 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.92 | 100.00 | 68.75 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.05 | 100.00 | 69.16 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.13 | 100.00 | 69.40 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.20 | 100.00 | 69.60 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 83.02 | 83.02 | ||
| mux_fle_3_in_5 | 83.96 | 83.96 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 84.91 | 84.91 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 83.02 | 83.02 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 82.08 | 82.08 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 86.99 | 86.99 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 83.02 | 83.02 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 83.96 | 83.96 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.11 | 65.11 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.39 | 100.00 | 70.17 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_8__7_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.92 | 100.00 | 68.75 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.94 | 100.00 | 68.81 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.93 | 100.00 | 68.78 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.94 | 100.00 | 68.83 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 78.30 | 78.30 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 87.67 | 87.67 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 86.79 | 86.79 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 85.85 | 85.85 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 86.79 | 86.79 | ||
| mux_fle_5_clk_0 | 64.71 | 64.71 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 83.96 | 83.96 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.87 | 64.87 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.32 | 100.00 | 69.97 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_8__8_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.08 | 100.00 | 69.25 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.96 | 100.00 | 68.89 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.13 | 100.00 | 69.38 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.59 | 100.00 | 67.76 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.10 | 100.00 | 69.30 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 83.96 | 83.96 | ||
| mux_fle_3_in_5 | 85.85 | 85.85 | ||
| mux_fle_4_clk_0 | 64.71 | 64.71 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 61.76 | 61.76 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 82.08 | 82.08 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 78.30 | 78.30 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 88.36 | 88.36 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.31 | 65.31 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.62 | 100.00 | 70.86 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.37 | 81.37 | grid_clb_8__9_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.18 | 100.00 | 69.55 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.46 | 100.00 | 70.38 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.59 | 100.00 | 70.78 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.28 | 100.00 | 69.83 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.63 | 100.00 | 70.89 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.17 | 100.00 | 69.50 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.63 | 100.00 | 70.89 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.44 | 100.00 | 70.33 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.02 | 83.02 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 81.13 | 81.13 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 82.08 | 82.08 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 83.96 | 83.96 | ||
| mux_fle_3_in_5 | 83.96 | 83.96 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 83.96 | 83.96 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 86.30 | 86.30 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 83.96 | 83.96 | ||
| mux_fle_6_in_5 | 86.79 | 86.79 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 83.02 | 83.02 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 84.91 | 84.91 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.90 | 64.90 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.35 | 100.00 | 70.04 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_8__10_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.65 | 100.00 | 67.94 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.04 | 100.00 | 69.12 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.88 | 100.00 | 68.65 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.89 | 100.00 | 68.68 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.30 | 100.00 | 69.91 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.12 | 100.00 | 69.35 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.08 | 100.00 | 69.25 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.11 | 100.00 | 69.34 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 86.99 | 86.99 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 80.19 | 80.19 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 83.96 | 83.96 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 86.99 | 86.99 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 88.36 | 88.36 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 64.71 | 64.71 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 83.96 | 83.96 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 83.02 | 83.02 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.82 | 64.82 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.29 | 100.00 | 69.88 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_8__11_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.68 | 100.00 | 68.04 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.13 | 100.00 | 69.40 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.28 | 100.00 | 69.83 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.71 | 100.00 | 68.12 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.90 | 100.00 | 68.71 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.84 | 100.00 | 68.53 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.94 | 100.00 | 68.83 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 86.99 | 86.99 | ||
| mux_fle_0_in_1 | 86.99 | 86.99 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 86.79 | 86.79 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 83.96 | 83.96 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 83.02 | 83.02 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 83.02 | 83.02 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 83.96 | 83.96 | ||
| mux_fle_6_clk_0 | 61.76 | 61.76 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 86.79 | 86.79 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 88.36 | 88.36 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 88.36 | 88.36 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 86.99 | 86.99 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 84.91 | 84.91 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.62 | 64.62 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.30 | 100.00 | 69.90 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.39 | 80.39 | grid_clb_8__12_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.86 | 100.00 | 68.58 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.89 | 100.00 | 68.66 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.08 | 100.00 | 69.24 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.04 | 100.00 | 69.12 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.17 | 100.00 | 69.50 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.98 | 100.00 | 68.93 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.20 | 100.00 | 69.60 | 80.00 |
| mem_fle_0_cin_0 | 78.69 | 100.00 | 56.06 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_7_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mux_fle_0_cin_0 | 4.55 | 4.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 88.36 | 88.36 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 77.36 | 77.36 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 77.36 | 77.36 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 82.08 | 82.08 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 87.67 | 87.67 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 76.42 | 76.42 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 76.42 | 76.42 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 83.02 | 83.02 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 79.25 | 79.25 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 81.13 | 81.13 | ||
| mux_fle_7_clk_0 | 61.76 | 61.76 | ||
| mux_fle_7_in_0 | 86.30 | 86.30 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 78.30 | 78.30 | ||
| mux_fle_8_clk_0 | 64.71 | 64.71 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 81.13 | 81.13 | ||
| mux_fle_9_in_5 | 80.19 | 80.19 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.76 | 64.76 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.32 | 100.00 | 69.96 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_10__1_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.74 | 100.00 | 68.21 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.34 | 100.00 | 70.01 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.97 | 100.00 | 68.91 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.86 | 100.00 | 68.58 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.24 | 100.00 | 69.71 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 82.08 | 82.08 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 76.42 | 76.42 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 88.36 | 88.36 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 83.02 | 83.02 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 82.08 | 82.08 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 81.13 | 81.13 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 73.58 | 73.58 | ||
| mux_fle_3_clk_0 | 61.76 | 61.76 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 82.08 | 82.08 | ||
| mux_fle_3_in_4 | 83.02 | 83.02 | ||
| mux_fle_3_in_5 | 79.25 | 79.25 | ||
| mux_fle_4_clk_0 | 61.76 | 61.76 | ||
| mux_fle_4_in_0 | 87.67 | 87.67 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 88.36 | 88.36 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 76.42 | 76.42 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 86.99 | 86.99 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 82.08 | 82.08 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 83.96 | 83.96 | ||
| mux_fle_6_in_5 | 74.53 | 74.53 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 88.36 | 88.36 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 81.13 | 81.13 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 87.67 | 87.67 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 80.19 | 80.19 | ||
| mux_fle_8_in_5 | 71.70 | 71.70 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 87.67 | 87.67 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.95 | 64.95 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.44 | 100.00 | 70.32 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_10__2_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.90 | 100.00 | 68.71 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.10 | 100.00 | 69.29 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.31 | 100.00 | 69.94 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.13 | 100.00 | 69.40 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.48 | 100.00 | 70.45 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.26 | 100.00 | 69.78 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.16 | 100.00 | 69.47 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.38 | 100.00 | 70.14 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_1_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 78.72 | 100.00 | 56.17 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mux_fle_0_cin_0 | 45.45 | 45.45 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.02 | 83.02 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 61.76 | 61.76 | ||
| mux_fle_1_in_0 | 86.30 | 86.30 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 78.30 | 78.30 | ||
| mux_fle_2_clk_0 | 61.76 | 61.76 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 80.19 | 80.19 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 87.67 | 87.67 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 81.13 | 81.13 | ||
| mux_fle_3_in_5 | 83.96 | 83.96 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 82.08 | 82.08 | ||
| mux_fle_4_in_5 | 70.75 | 70.75 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 82.08 | 82.08 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 78.30 | 78.30 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 83.02 | 83.02 | ||
| mux_fle_9_in_5 | 80.19 | 80.19 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.95 | 64.95 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.36 | 100.00 | 70.09 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_10__3_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.75 | 100.00 | 68.25 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.98 | 100.00 | 68.94 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.23 | 100.00 | 69.70 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.22 | 100.00 | 69.66 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.18 | 100.00 | 69.53 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.00 | 100.00 | 69.01 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_7_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 87.67 | 87.67 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 75.47 | 75.47 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 86.79 | 86.79 | ||
| mux_fle_1_in_5 | 78.30 | 78.30 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 83.96 | 83.96 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 83.96 | 83.96 | ||
| mux_fle_3_in_5 | 80.19 | 80.19 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 83.96 | 83.96 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 83.02 | 83.02 | ||
| mux_fle_5_in_5 | 80.19 | 80.19 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 61.76 | 61.76 | ||
| mux_fle_7_in_0 | 87.67 | 87.67 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 72.64 | 72.64 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 82.08 | 82.08 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 88.36 | 88.36 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 80.19 | 80.19 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.33 | 65.33 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.51 | 100.00 | 70.53 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_10__4_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.44 | 100.00 | 70.33 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.53 | 100.00 | 70.58 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.97 | 100.00 | 68.91 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.18 | 100.00 | 69.55 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.98 | 100.00 | 68.94 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.23 | 100.00 | 69.70 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.17 | 100.00 | 69.52 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 82.08 | 82.08 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 84.91 | 84.91 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 86.99 | 86.99 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 82.08 | 82.08 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 79.25 | 79.25 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.80 | 64.80 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.38 | 100.00 | 70.13 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__5_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.16 | 100.00 | 69.47 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.26 | 100.00 | 69.78 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.81 | 100.00 | 68.43 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.12 | 100.00 | 69.35 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.96 | 100.00 | 68.89 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.16 | 100.00 | 69.48 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.13 | 100.00 | 69.38 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 88.36 | 88.36 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 84.91 | 84.91 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 80.19 | 80.19 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 83.96 | 83.96 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 86.79 | 86.79 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 82.08 | 82.08 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 83.96 | 83.96 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 87.67 | 87.67 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 61.76 | 61.76 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 86.79 | 86.79 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 83.96 | 83.96 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.82 | 64.82 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.27 | 100.00 | 69.80 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__6_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.72 | 100.00 | 68.17 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.69 | 100.00 | 68.06 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.37 | 100.00 | 70.12 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.94 | 100.00 | 68.83 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.87 | 100.00 | 68.61 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.74 | 100.00 | 68.22 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.79 | 100.00 | 68.37 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.86 | 100.00 | 68.57 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 61.76 | 61.76 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 80.19 | 80.19 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 83.02 | 83.02 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 85.85 | 85.85 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 87.67 | 87.67 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 82.08 | 82.08 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 87.67 | 87.67 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 82.08 | 82.08 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 83.96 | 83.96 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.82 | 64.82 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.38 | 100.00 | 70.13 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__7_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.02 | 100.00 | 69.06 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.25 | 100.00 | 69.76 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.70 | 100.00 | 68.09 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.24 | 100.00 | 69.71 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.96 | 100.00 | 68.88 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.10 | 100.00 | 69.29 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.14 | 100.00 | 69.42 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.20 | 100.00 | 69.61 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 87.67 | 87.67 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 84.91 | 84.91 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 88.36 | 88.36 | ||
| mux_fle_1_in_1 | 86.99 | 86.99 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 85.85 | 85.85 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 83.96 | 83.96 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 83.96 | 83.96 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 82.08 | 82.08 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 88.36 | 88.36 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 80.19 | 80.19 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 87.67 | 87.67 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 89.04 | 89.04 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.03 | 65.03 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.44 | 100.00 | 70.32 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.88 | 80.88 | grid_clb_10__8_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.23 | 100.00 | 69.68 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.43 | 100.00 | 70.28 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.18 | 100.00 | 69.55 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.13 | 100.00 | 69.38 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.24 | 100.00 | 69.73 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.98 | 100.00 | 68.94 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.98 | 100.00 | 68.94 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 80.19 | 80.19 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 83.02 | 83.02 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 86.99 | 86.99 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 88.36 | 88.36 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 83.02 | 83.02 | ||
| mux_fle_4_in_5 | 83.96 | 83.96 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 84.91 | 84.91 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 86.79 | 86.79 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 83.02 | 83.02 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 88.36 | 88.36 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.95 | 64.95 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.39 | 100.00 | 70.18 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__9_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.10 | 100.00 | 69.29 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.17 | 100.00 | 69.50 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.29 | 100.00 | 69.86 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.10 | 100.00 | 69.29 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.10 | 100.00 | 69.29 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.08 | 100.00 | 69.25 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.12 | 100.00 | 69.35 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.53 | 100.00 | 67.60 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 45.45 | 45.45 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 84.91 | 84.91 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 83.96 | 83.96 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 86.79 | 86.79 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 86.79 | 86.79 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 81.13 | 81.13 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 83.96 | 83.96 | ||
| mux_fle_8_clk_0 | 61.76 | 61.76 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 86.99 | 86.99 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.79 | 64.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.28 | 100.00 | 69.83 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__10_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.64 | 100.00 | 67.91 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.69 | 100.00 | 68.07 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.04 | 100.00 | 69.11 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.57 | 100.00 | 67.71 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.05 | 100.00 | 69.14 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.14 | 100.00 | 69.42 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.97 | 100.00 | 68.91 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.08 | 100.00 | 69.24 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 76.87 | 100.00 | 50.62 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 88.36 | 88.36 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 72.64 | 72.64 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 88.36 | 88.36 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 67.92 | 67.92 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 80.19 | 80.19 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 83.02 | 83.02 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 64.71 | 64.71 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 86.79 | 86.79 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 81.13 | 81.13 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 82.08 | 82.08 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 80.19 | 80.19 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 88.36 | 88.36 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 83.96 | 83.96 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.74 | 64.74 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.32 | 100.00 | 69.97 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_10__11_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.87 | 100.00 | 68.61 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.08 | 100.00 | 69.25 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.88 | 100.00 | 68.65 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.90 | 100.00 | 68.71 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.97 | 100.00 | 68.91 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.98 | 100.00 | 68.93 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 78.11 | 100.00 | 54.32 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 87.67 | 87.67 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 80.19 | 80.19 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 86.79 | 86.79 | ||
| mux_fle_1_in_5 | 82.08 | 82.08 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 81.13 | 81.13 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 87.67 | 87.67 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 83.96 | 83.96 | ||
| mux_fle_3_in_5 | 73.58 | 73.58 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 83.96 | 83.96 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 81.13 | 81.13 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 87.67 | 87.67 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 79.25 | 79.25 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 82.08 | 82.08 | ||
| mux_fle_7_in_4 | 83.02 | 83.02 | ||
| mux_fle_7_in_5 | 71.70 | 71.70 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 83.02 | 83.02 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 85.85 | 85.85 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 82.08 | 82.08 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.49 | 64.49 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.13 | 100.00 | 69.40 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 79.66 | 79.66 | grid_clb_10__12_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.28 | 100.00 | 66.83 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.80 | 100.00 | 68.40 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.04 | 100.00 | 69.12 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.93 | 100.00 | 68.78 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.78 | 100.00 | 68.34 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.02 | 100.00 | 69.07 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.82 | 100.00 | 68.47 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.20 | 100.00 | 69.60 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 78.11 | 100.00 | 54.32 | 80.00 |
| mem_fle_2_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 78.72 | 100.00 | 56.17 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mux_fle_0_cin_0 | 9.09 | 9.09 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 86.99 | 86.99 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 85.62 | 85.62 | ||
| mux_fle_0_in_3 | 81.13 | 81.13 | ||
| mux_fle_0_in_4 | 80.19 | 80.19 | ||
| mux_fle_0_in_5 | 76.42 | 76.42 | ||
| mux_fle_1_clk_0 | 61.76 | 61.76 | ||
| mux_fle_1_in_0 | 86.30 | 86.30 | ||
| mux_fle_1_in_1 | 87.67 | 87.67 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 81.13 | 81.13 | ||
| mux_fle_1_in_4 | 78.30 | 78.30 | ||
| mux_fle_1_in_5 | 68.87 | 68.87 | ||
| mux_fle_2_clk_0 | 64.71 | 64.71 | ||
| mux_fle_2_in_0 | 87.67 | 87.67 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 71.70 | 71.70 | ||
| mux_fle_2_in_5 | 81.13 | 81.13 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 82.88 | 82.88 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 81.13 | 81.13 | ||
| mux_fle_3_in_4 | 81.13 | 81.13 | ||
| mux_fle_3_in_5 | 76.42 | 76.42 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 87.67 | 87.67 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 88.36 | 88.36 | ||
| mux_fle_4_in_3 | 83.02 | 83.02 | ||
| mux_fle_4_in_4 | 73.58 | 73.58 | ||
| mux_fle_4_in_5 | 75.47 | 75.47 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 86.30 | 86.30 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 83.02 | 83.02 | ||
| mux_fle_5_in_4 | 81.13 | 81.13 | ||
| mux_fle_5_in_5 | 81.13 | 81.13 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 86.30 | 86.30 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 81.13 | 81.13 | ||
| mux_fle_6_in_4 | 81.13 | 81.13 | ||
| mux_fle_6_in_5 | 77.36 | 77.36 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 87.67 | 87.67 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 83.02 | 83.02 | ||
| mux_fle_7_in_4 | 80.19 | 80.19 | ||
| mux_fle_7_in_5 | 69.81 | 69.81 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 87.67 | 87.67 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 83.02 | 83.02 | ||
| mux_fle_8_in_4 | 80.19 | 80.19 | ||
| mux_fle_8_in_5 | 80.19 | 80.19 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 88.36 | 88.36 | ||
| mux_fle_9_in_3 | 76.42 | 76.42 | ||
| mux_fle_9_in_4 | 80.19 | 80.19 | ||
| mux_fle_9_in_5 | 80.19 | 80.19 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.21 | 65.21 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.45 | 100.00 | 70.35 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.37 | 81.37 | grid_clb_11__1_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.87 | 100.00 | 68.61 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.24 | 100.00 | 69.73 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.34 | 100.00 | 70.02 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.34 | 100.00 | 70.01 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.33 | 100.00 | 69.99 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.23 | 100.00 | 69.70 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.58 | 100.00 | 70.73 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.91 | 100.00 | 68.73 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.98 | 100.00 | 68.93 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 87.67 | 87.67 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 83.96 | 83.96 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 87.67 | 87.67 | ||
| mux_fle_1_in_3 | 82.08 | 82.08 | ||
| mux_fle_1_in_4 | 78.30 | 78.30 | ||
| mux_fle_1_in_5 | 81.13 | 81.13 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 88.36 | 88.36 | ||
| mux_fle_2_in_1 | 86.99 | 86.99 | ||
| mux_fle_2_in_2 | 87.67 | 87.67 | ||
| mux_fle_2_in_3 | 82.08 | 82.08 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 78.30 | 78.30 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 87.67 | 87.67 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 86.30 | 86.30 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 82.08 | 82.08 | ||
| mux_fle_3_in_5 | 74.53 | 74.53 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 87.67 | 87.67 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 81.13 | 81.13 | ||
| mux_fle_4_in_4 | 82.08 | 82.08 | ||
| mux_fle_4_in_5 | 79.25 | 79.25 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 87.67 | 87.67 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 82.08 | 82.08 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 81.13 | 81.13 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 87.67 | 87.67 | ||
| mux_fle_6_in_2 | 86.30 | 86.30 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 80.19 | 80.19 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 83.02 | 83.02 | ||
| mux_fle_8_clk_0 | 61.76 | 61.76 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 86.99 | 86.99 | ||
| mux_fle_8_in_2 | 86.99 | 86.99 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 83.02 | 83.02 | ||
| mux_fle_8_in_5 | 79.25 | 79.25 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 76.42 | 76.42 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.83 | 64.83 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.34 | 100.00 | 70.02 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.37 | 81.37 | grid_clb_11__2_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.74 | 100.00 | 68.21 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.16 | 100.00 | 69.47 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.94 | 100.00 | 68.83 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.95 | 100.00 | 68.84 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.51 | 100.00 | 70.53 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.92 | 100.00 | 68.75 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.18 | 100.00 | 69.55 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.16 | 100.00 | 69.47 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 78.11 | 100.00 | 54.32 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 79.25 | 79.25 | ||
| mux_fle_0_in_5 | 77.36 | 77.36 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 88.36 | 88.36 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 80.19 | 80.19 | ||
| mux_fle_1_in_5 | 69.81 | 69.81 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 81.13 | 81.13 | ||
| mux_fle_2_in_5 | 71.70 | 71.70 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 79.25 | 79.25 | ||
| mux_fle_4_clk_0 | 64.71 | 64.71 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 82.08 | 82.08 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 87.67 | 87.67 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 84.91 | 84.91 | ||
| mux_fle_6_in_4 | 83.02 | 83.02 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 61.76 | 61.76 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 81.13 | 81.13 | ||
| mux_fle_7_in_4 | 83.02 | 83.02 | ||
| mux_fle_7_in_5 | 79.25 | 79.25 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 87.67 | 87.67 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 81.13 | 81.13 | ||
| mux_fle_8_in_5 | 75.47 | 75.47 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 81.13 | 81.13 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.02 | 65.02 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.42 | 100.00 | 70.27 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_11__3_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.01 | 100.00 | 69.04 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.23 | 100.00 | 69.70 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.96 | 100.00 | 68.89 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.21 | 100.00 | 69.63 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.33 | 100.00 | 69.99 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.14 | 100.00 | 69.43 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.19 | 100.00 | 69.58 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 88.36 | 88.36 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 81.13 | 81.13 | ||
| mux_fle_0_in_5 | 77.36 | 77.36 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 83.02 | 83.02 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 79.25 | 79.25 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 87.67 | 87.67 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 84.91 | 84.91 | ||
| mux_fle_3_in_4 | 81.13 | 81.13 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 83.02 | 83.02 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 81.13 | 81.13 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 83.02 | 83.02 | ||
| mux_fle_5_in_5 | 83.02 | 83.02 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.04 | 89.04 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 89.73 | 89.73 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 81.13 | 81.13 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 71.70 | 71.70 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 84.91 | 84.91 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.94 | 64.94 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.41 | 100.00 | 70.24 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_11__4_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.06 | 100.00 | 69.17 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.08 | 100.00 | 69.24 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.02 | 100.00 | 69.06 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.16 | 100.00 | 69.47 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.25 | 100.00 | 69.74 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.12 | 100.00 | 69.35 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 83.96 | 83.96 | ||
| mux_fle_0_in_4 | 78.30 | 78.30 | ||
| mux_fle_0_in_5 | 82.08 | 82.08 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 86.99 | 86.99 | ||
| mux_fle_1_in_1 | 86.99 | 86.99 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 86.79 | 86.79 | ||
| mux_fle_1_in_5 | 77.36 | 77.36 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 82.08 | 82.08 | ||
| mux_fle_2_in_5 | 80.19 | 80.19 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 80.19 | 80.19 | ||
| mux_fle_3_in_5 | 81.13 | 81.13 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 80.19 | 80.19 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 84.91 | 84.91 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 83.02 | 83.02 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 88.36 | 88.36 | ||
| mux_fle_7_in_2 | 87.67 | 87.67 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 83.96 | 83.96 | ||
| mux_fle_8_clk_0 | 64.71 | 64.71 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 87.67 | 87.67 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 83.02 | 83.02 | ||
| mux_fle_8_in_5 | 82.08 | 82.08 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.17 | 65.17 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.51 | 100.00 | 70.54 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_11__5_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.28 | 100.00 | 69.84 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.04 | 100.00 | 69.11 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.33 | 100.00 | 69.99 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.29 | 100.00 | 69.86 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.28 | 100.00 | 69.84 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.48 | 100.00 | 70.43 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.19 | 100.00 | 69.56 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.20 | 100.00 | 69.60 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.02 | 100.00 | 69.06 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 83.96 | 83.96 | ||
| mux_fle_1_clk_0 | 64.71 | 64.71 | ||
| mux_fle_1_in_0 | 87.67 | 87.67 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 79.25 | 79.25 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 86.99 | 86.99 | ||
| mux_fle_2_in_2 | 86.99 | 86.99 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 86.79 | 86.79 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 84.91 | 84.91 | ||
| mux_fle_4_clk_0 | 64.71 | 64.71 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 85.85 | 85.85 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 87.67 | 87.67 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 88.36 | 88.36 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 84.91 | 84.91 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 88.36 | 88.36 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.84 | 64.84 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.30 | 100.00 | 69.90 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__6_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.71 | 100.00 | 68.14 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.04 | 100.00 | 69.12 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.49 | 100.00 | 67.47 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.95 | 100.00 | 68.84 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.23 | 100.00 | 69.68 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.14 | 100.00 | 69.42 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.95 | 100.00 | 68.84 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 89.73 | 89.73 | ||
| mux_fle_0_in_3 | 84.91 | 84.91 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 78.30 | 78.30 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.04 | 89.04 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 80.19 | 80.19 | ||
| mux_fle_2_clk_0 | 64.71 | 64.71 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 87.67 | 87.67 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 74.53 | 74.53 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 83.96 | 83.96 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 86.79 | 86.79 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 87.67 | 87.67 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 89.04 | 89.04 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 84.91 | 84.91 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 84.91 | 84.91 | ||
| mux_fle_6_in_4 | 86.79 | 86.79 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 64.71 | 64.71 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 88.36 | 88.36 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 76.42 | 76.42 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.68 | 64.68 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.29 | 100.00 | 69.86 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__7_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.81 | 100.00 | 68.42 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.89 | 100.00 | 68.68 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.78 | 100.00 | 68.34 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.89 | 100.00 | 68.68 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.14 | 100.00 | 69.43 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.02 | 100.00 | 69.07 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.89 | 100.00 | 68.68 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 84.91 | 84.91 | ||
| mux_fle_0_in_5 | 75.47 | 75.47 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.04 | 89.04 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 83.02 | 83.02 | ||
| mux_fle_2_in_5 | 78.30 | 78.30 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 83.96 | 83.96 | ||
| mux_fle_3_in_4 | 83.02 | 83.02 | ||
| mux_fle_3_in_5 | 75.47 | 75.47 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 86.79 | 86.79 | ||
| mux_fle_4_in_5 | 84.91 | 84.91 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 88.36 | 88.36 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 83.96 | 83.96 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 89.04 | 89.04 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 81.13 | 81.13 | ||
| mux_fle_6_in_5 | 84.91 | 84.91 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 83.02 | 83.02 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 87.67 | 87.67 | ||
| mux_fle_8_in_2 | 88.36 | 88.36 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 75.47 | 75.47 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 83.96 | 83.96 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 83.96 | 83.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.91 | 64.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.38 | 100.00 | 70.14 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__8_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.07 | 100.00 | 69.22 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.21 | 100.00 | 69.63 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.92 | 100.00 | 68.76 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.20 | 100.00 | 69.61 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.30 | 100.00 | 69.89 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.11 | 100.00 | 69.32 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.77 | 100.00 | 68.30 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 87.67 | 87.67 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 79.25 | 79.25 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 86.99 | 86.99 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 84.91 | 84.91 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 81.13 | 81.13 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 90.41 | 90.41 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.73 | 89.73 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 84.91 | 84.91 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.04 | 89.04 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 85.85 | 85.85 | ||
| mux_fle_4_in_5 | 83.96 | 83.96 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 82.08 | 82.08 | ||
| mux_fle_5_in_4 | 84.91 | 84.91 | ||
| mux_fle_5_in_5 | 80.19 | 80.19 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.04 | 89.04 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 85.85 | 85.85 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 90.41 | 90.41 | ||
| mux_fle_7_in_2 | 88.36 | 88.36 | ||
| mux_fle_7_in_3 | 83.96 | 83.96 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 90.41 | 90.41 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.81 | 64.81 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.28 | 100.00 | 69.84 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__9_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.61 | 100.00 | 67.83 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.83 | 100.00 | 68.48 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.90 | 100.00 | 68.71 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.01 | 100.00 | 69.04 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.13 | 100.00 | 69.38 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.95 | 100.00 | 68.86 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.95 | 100.00 | 68.86 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 84.91 | 84.91 | ||
| mux_fle_0_in_4 | 83.02 | 83.02 | ||
| mux_fle_0_in_5 | 77.36 | 77.36 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 90.41 | 90.41 | ||
| mux_fle_1_in_1 | 89.73 | 89.73 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 83.96 | 83.96 | ||
| mux_fle_1_in_5 | 81.13 | 81.13 | ||
| mux_fle_2_clk_0 | 61.76 | 61.76 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 85.85 | 85.85 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 85.85 | 85.85 | ||
| mux_fle_3_clk_0 | 61.76 | 61.76 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 82.08 | 82.08 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 79.25 | 79.25 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 89.04 | 89.04 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 86.79 | 86.79 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 86.79 | 86.79 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 85.85 | 85.85 | ||
| mux_fle_6_in_4 | 85.85 | 85.85 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 86.79 | 86.79 | ||
| mux_fle_7_in_4 | 85.85 | 85.85 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 88.36 | 88.36 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 89.73 | 89.73 | ||
| mux_fle_8_in_3 | 82.08 | 82.08 | ||
| mux_fle_8_in_4 | 84.91 | 84.91 | ||
| mux_fle_8_in_5 | 84.91 | 84.91 | ||
| mux_fle_9_clk_0 | 61.76 | 61.76 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 87.67 | 87.67 | ||
| mux_fle_9_in_3 | 83.02 | 83.02 | ||
| mux_fle_9_in_4 | 86.79 | 86.79 | ||
| mux_fle_9_in_5 | 82.08 | 82.08 |
| SCORE | LINE | TOGGLE | BRANCH |
| 65.11 | 65.11 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.46 | 100.00 | 70.37 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__10_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.95 | 100.00 | 68.86 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.32 | 100.00 | 69.97 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.20 | 100.00 | 69.60 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.01 | 100.00 | 69.04 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.11 | 100.00 | 69.34 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.30 | 100.00 | 69.91 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.13 | 100.00 | 69.40 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.09 | 100.00 | 69.27 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.30 | 100.00 | 69.91 | 80.00 |
| mem_fle_0_cin_0 | 80.20 | 100.00 | 60.61 | 80.00 |
| mem_fle_0_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_4_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 45.45 | 45.45 | ||
| mux_fle_0_clk_0 | 61.76 | 61.76 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 88.36 | 88.36 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 86.79 | 86.79 | ||
| mux_fle_0_in_5 | 77.36 | 77.36 | ||
| mux_fle_1_clk_0 | 61.76 | 61.76 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 85.85 | 85.85 | ||
| mux_fle_1_in_4 | 85.85 | 85.85 | ||
| mux_fle_1_in_5 | 86.79 | 86.79 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 86.79 | 86.79 | ||
| mux_fle_2_in_5 | 84.91 | 84.91 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 90.41 | 90.41 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 89.04 | 89.04 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 86.79 | 86.79 | ||
| mux_fle_3_in_5 | 79.25 | 79.25 | ||
| mux_fle_4_clk_0 | 70.59 | 70.59 | ||
| mux_fle_4_in_0 | 90.41 | 90.41 | ||
| mux_fle_4_in_1 | 89.73 | 89.73 | ||
| mux_fle_4_in_2 | 88.36 | 88.36 | ||
| mux_fle_4_in_3 | 86.79 | 86.79 | ||
| mux_fle_4_in_4 | 82.08 | 82.08 | ||
| mux_fle_4_in_5 | 83.02 | 83.02 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 90.41 | 90.41 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 85.85 | 85.85 | ||
| mux_fle_5_in_5 | 82.08 | 82.08 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 90.41 | 90.41 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 88.36 | 88.36 | ||
| mux_fle_6_in_3 | 84.91 | 84.91 | ||
| mux_fle_6_in_4 | 84.91 | 84.91 | ||
| mux_fle_6_in_5 | 80.19 | 80.19 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 89.73 | 89.73 | ||
| mux_fle_7_in_1 | 86.99 | 86.99 | ||
| mux_fle_7_in_2 | 90.41 | 90.41 | ||
| mux_fle_7_in_3 | 81.13 | 81.13 | ||
| mux_fle_7_in_4 | 82.08 | 82.08 | ||
| mux_fle_7_in_5 | 81.13 | 81.13 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 90.41 | 90.41 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 80.19 | 80.19 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 84.91 | 84.91 | ||
| mux_fle_9_in_5 | 85.85 | 85.85 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.62 | 64.62 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.31 | 100.00 | 69.94 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.13 | 81.13 | grid_clb_11__11_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.94 | 100.00 | 68.81 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.07 | 100.00 | 69.20 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.01 | 100.00 | 69.02 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.96 | 100.00 | 68.89 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.22 | 100.00 | 69.65 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.87 | 100.00 | 68.61 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.02 | 100.00 | 69.06 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.33 | 100.00 | 69.99 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.82 | 100.00 | 68.47 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 87.67 | 87.67 | ||
| mux_fle_0_in_2 | 90.41 | 90.41 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 80.19 | 80.19 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 89.04 | 89.04 | ||
| mux_fle_1_in_2 | 89.04 | 89.04 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 84.91 | 84.91 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 67.65 | 67.65 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 88.36 | 88.36 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 83.96 | 83.96 | ||
| mux_fle_2_in_4 | 85.85 | 85.85 | ||
| mux_fle_2_in_5 | 77.36 | 77.36 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 90.41 | 90.41 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 82.08 | 82.08 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 80.19 | 80.19 | ||
| mux_fle_4_clk_0 | 61.76 | 61.76 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 90.41 | 90.41 | ||
| mux_fle_4_in_3 | 83.96 | 83.96 | ||
| mux_fle_4_in_4 | 84.91 | 84.91 | ||
| mux_fle_4_in_5 | 72.64 | 72.64 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 87.67 | 87.67 | ||
| mux_fle_5_in_1 | 89.04 | 89.04 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 83.96 | 83.96 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 78.30 | 78.30 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 90.41 | 90.41 | ||
| mux_fle_6_in_3 | 84.91 | 84.91 | ||
| mux_fle_6_in_4 | 81.13 | 81.13 | ||
| mux_fle_6_in_5 | 76.42 | 76.42 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 87.67 | 87.67 | ||
| mux_fle_7_in_2 | 87.67 | 87.67 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 86.79 | 86.79 | ||
| mux_fle_7_in_5 | 78.30 | 78.30 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 89.73 | 89.73 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 85.85 | 85.85 | ||
| mux_fle_8_in_4 | 85.85 | 85.85 | ||
| mux_fle_8_in_5 | 83.96 | 83.96 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 90.41 | 90.41 | ||
| mux_fle_9_in_3 | 80.19 | 80.19 | ||
| mux_fle_9_in_4 | 85.85 | 85.85 | ||
| mux_fle_9_in_5 | 84.91 | 84.91 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.42 | 64.42 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.05 | 100.00 | 69.14 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 79.41 | 79.41 | grid_clb_11__12_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.46 | 100.00 | 67.39 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.74 | 100.00 | 68.22 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.93 | 100.00 | 68.78 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.99 | 100.00 | 68.98 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.83 | 100.00 | 68.48 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.97 | 100.00 | 68.91 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.41 | 100.00 | 67.22 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.24 | 100.00 | 69.71 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.92 | 100.00 | 68.75 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.75 | 100.00 | 68.25 | 80.00 |
| mem_fle_0_cin_0 | 78.69 | 100.00 | 56.06 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mux_fle_0_cin_0 | 4.55 | 4.55 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 84.25 | 84.25 | ||
| mux_fle_0_in_1 | 89.73 | 89.73 | ||
| mux_fle_0_in_2 | 86.99 | 86.99 | ||
| mux_fle_0_in_3 | 81.13 | 81.13 | ||
| mux_fle_0_in_4 | 81.13 | 81.13 | ||
| mux_fle_0_in_5 | 84.91 | 84.91 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 84.25 | 84.25 | ||
| mux_fle_1_in_1 | 88.36 | 88.36 | ||
| mux_fle_1_in_2 | 89.73 | 89.73 | ||
| mux_fle_1_in_3 | 79.25 | 79.25 | ||
| mux_fle_1_in_4 | 80.19 | 80.19 | ||
| mux_fle_1_in_5 | 85.85 | 85.85 | ||
| mux_fle_2_clk_0 | 64.71 | 64.71 | ||
| mux_fle_2_in_0 | 85.62 | 85.62 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 88.36 | 88.36 | ||
| mux_fle_2_in_3 | 71.70 | 71.70 | ||
| mux_fle_2_in_4 | 75.47 | 75.47 | ||
| mux_fle_2_in_5 | 72.64 | 72.64 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 82.19 | 82.19 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 89.73 | 89.73 | ||
| mux_fle_3_in_3 | 76.42 | 76.42 | ||
| mux_fle_3_in_4 | 80.19 | 80.19 | ||
| mux_fle_3_in_5 | 83.02 | 83.02 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 84.25 | 84.25 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 80.19 | 80.19 | ||
| mux_fle_4_in_4 | 79.25 | 79.25 | ||
| mux_fle_4_in_5 | 72.64 | 72.64 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 82.19 | 82.19 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 80.19 | 80.19 | ||
| mux_fle_5_in_4 | 75.47 | 75.47 | ||
| mux_fle_5_in_5 | 77.36 | 77.36 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 84.25 | 84.25 | ||
| mux_fle_6_in_1 | 89.73 | 89.73 | ||
| mux_fle_6_in_2 | 87.67 | 87.67 | ||
| mux_fle_6_in_3 | 74.53 | 74.53 | ||
| mux_fle_6_in_4 | 80.19 | 80.19 | ||
| mux_fle_6_in_5 | 72.64 | 72.64 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 85.62 | 85.62 | ||
| mux_fle_7_in_1 | 89.04 | 89.04 | ||
| mux_fle_7_in_2 | 87.67 | 87.67 | ||
| mux_fle_7_in_3 | 81.13 | 81.13 | ||
| mux_fle_7_in_4 | 79.25 | 79.25 | ||
| mux_fle_7_in_5 | 74.53 | 74.53 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 82.19 | 82.19 | ||
| mux_fle_8_in_1 | 89.04 | 89.04 | ||
| mux_fle_8_in_2 | 89.04 | 89.04 | ||
| mux_fle_8_in_3 | 81.13 | 81.13 | ||
| mux_fle_8_in_4 | 76.42 | 76.42 | ||
| mux_fle_8_in_5 | 71.70 | 71.70 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 82.19 | 82.19 | ||
| mux_fle_9_in_1 | 89.04 | 89.04 | ||
| mux_fle_9_in_2 | 87.67 | 87.67 | ||
| mux_fle_9_in_3 | 81.13 | 81.13 | ||
| mux_fle_9_in_4 | 72.64 | 72.64 | ||
| mux_fle_9_in_5 | 72.64 | 72.64 |
| SCORE | LINE | TOGGLE | BRANCH |
| 63.96 | 63.96 |
| SCORE | LINE | TOGGLE | BRANCH |
| 82.51 | 100.00 | 67.53 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 78.43 | 78.43 | grid_clb_12__1_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 50.00 | 50.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 0.00 | 0.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 33.33 | 33.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 50.00 | 50.00 | ||
| i_nand2_x1_and_rst | 66.67 | 66.67 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 81.51 | 100.00 | 64.52 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 82.25 | 100.00 | 66.76 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.51 | 100.00 | 67.53 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.59 | 100.00 | 67.76 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.33 | 100.00 | 66.99 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.41 | 100.00 | 67.22 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.46 | 100.00 | 67.37 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 82.40 | 100.00 | 67.21 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 82.59 | 100.00 | 67.76 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.57 | 100.00 | 67.70 | 80.00 |
| mem_fle_0_cin_0 | 78.69 | 100.00 | 56.06 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_3_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 13.64 | 13.64 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 76.03 | 76.03 | ||
| mux_fle_0_in_1 | 78.77 | 78.77 | ||
| mux_fle_0_in_2 | 78.08 | 78.08 | ||
| mux_fle_0_in_3 | 70.75 | 70.75 | ||
| mux_fle_0_in_4 | 69.81 | 69.81 | ||
| mux_fle_0_in_5 | 69.81 | 69.81 | ||
| mux_fle_1_clk_0 | 67.65 | 67.65 | ||
| mux_fle_1_in_0 | 75.34 | 75.34 | ||
| mux_fle_1_in_1 | 82.88 | 82.88 | ||
| mux_fle_1_in_2 | 79.45 | 79.45 | ||
| mux_fle_1_in_3 | 73.58 | 73.58 | ||
| mux_fle_1_in_4 | 66.98 | 66.98 | ||
| mux_fle_1_in_5 | 68.87 | 68.87 | ||
| mux_fle_2_clk_0 | 64.71 | 64.71 | ||
| mux_fle_2_in_0 | 77.40 | 77.40 | ||
| mux_fle_2_in_1 | 80.82 | 80.82 | ||
| mux_fle_2_in_2 | 86.30 | 86.30 | ||
| mux_fle_2_in_3 | 73.58 | 73.58 | ||
| mux_fle_2_in_4 | 65.09 | 65.09 | ||
| mux_fle_2_in_5 | 75.47 | 75.47 | ||
| mux_fle_3_clk_0 | 64.71 | 64.71 | ||
| mux_fle_3_in_0 | 74.66 | 74.66 | ||
| mux_fle_3_in_1 | 82.19 | 82.19 | ||
| mux_fle_3_in_2 | 82.88 | 82.88 | ||
| mux_fle_3_in_3 | 72.64 | 72.64 | ||
| mux_fle_3_in_4 | 66.04 | 66.04 | ||
| mux_fle_3_in_5 | 77.36 | 77.36 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 78.77 | 78.77 | ||
| mux_fle_4_in_1 | 85.62 | 85.62 | ||
| mux_fle_4_in_2 | 84.25 | 84.25 | ||
| mux_fle_4_in_3 | 71.70 | 71.70 | ||
| mux_fle_4_in_4 | 68.87 | 68.87 | ||
| mux_fle_4_in_5 | 79.25 | 79.25 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 75.34 | 75.34 | ||
| mux_fle_5_in_1 | 86.99 | 86.99 | ||
| mux_fle_5_in_2 | 86.30 | 86.30 | ||
| mux_fle_5_in_3 | 69.81 | 69.81 | ||
| mux_fle_5_in_4 | 71.70 | 71.70 | ||
| mux_fle_5_in_5 | 75.47 | 75.47 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 76.03 | 76.03 | ||
| mux_fle_6_in_1 | 85.62 | 85.62 | ||
| mux_fle_6_in_2 | 82.19 | 82.19 | ||
| mux_fle_6_in_3 | 68.87 | 68.87 | ||
| mux_fle_6_in_4 | 74.53 | 74.53 | ||
| mux_fle_6_in_5 | 68.87 | 68.87 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 78.77 | 78.77 | ||
| mux_fle_7_in_1 | 85.62 | 85.62 | ||
| mux_fle_7_in_2 | 85.62 | 85.62 | ||
| mux_fle_7_in_3 | 70.75 | 70.75 | ||
| mux_fle_7_in_4 | 63.21 | 63.21 | ||
| mux_fle_7_in_5 | 70.75 | 70.75 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 78.08 | 78.08 | ||
| mux_fle_8_in_1 | 83.56 | 83.56 | ||
| mux_fle_8_in_2 | 86.30 | 86.30 | ||
| mux_fle_8_in_3 | 69.81 | 69.81 | ||
| mux_fle_8_in_4 | 69.81 | 69.81 | ||
| mux_fle_8_in_5 | 78.30 | 78.30 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 76.03 | 76.03 | ||
| mux_fle_9_in_1 | 84.93 | 84.93 | ||
| mux_fle_9_in_2 | 87.67 | 87.67 | ||
| mux_fle_9_in_3 | 73.58 | 73.58 | ||
| mux_fle_9_in_4 | 72.64 | 72.64 | ||
| mux_fle_9_in_5 | 71.70 | 71.70 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.84 | 64.84 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.23 | 100.00 | 69.69 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 80.88 | 80.88 | grid_clb_12__2_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 0.00 | 0.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 0.00 | 0.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 0.00 | 0.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 0.00 | 0.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 0.00 | 0.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 0.00 | 0.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 0.00 | 0.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 0.00 | 0.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 0.00 | 0.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 0.00 | 0.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.81 | 100.00 | 68.42 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.01 | 100.00 | 69.02 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.00 | 100.00 | 69.01 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.03 | 100.00 | 69.09 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 82.81 | 100.00 | 68.42 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.71 | 100.00 | 68.14 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 82.82 | 100.00 | 68.47 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.12 | 100.00 | 69.37 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 82.81 | 100.00 | 68.43 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_1_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_1_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_3 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_2_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_3_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_5_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_8_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_8_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_9_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 67.65 | 67.65 | ||
| mux_fle_0_in_0 | 89.73 | 89.73 | ||
| mux_fle_0_in_1 | 90.41 | 90.41 | ||
| mux_fle_0_in_2 | 89.04 | 89.04 | ||
| mux_fle_0_in_3 | 82.08 | 82.08 | ||
| mux_fle_0_in_4 | 83.96 | 83.96 | ||
| mux_fle_0_in_5 | 81.13 | 81.13 | ||
| mux_fle_1_clk_0 | 61.76 | 61.76 | ||
| mux_fle_1_in_0 | 86.99 | 86.99 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 90.41 | 90.41 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 83.02 | 83.02 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 87.67 | 87.67 | ||
| mux_fle_2_in_1 | 89.04 | 89.04 | ||
| mux_fle_2_in_2 | 90.41 | 90.41 | ||
| mux_fle_2_in_3 | 81.13 | 81.13 | ||
| mux_fle_2_in_4 | 83.96 | 83.96 | ||
| mux_fle_2_in_5 | 83.02 | 83.02 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 88.36 | 88.36 | ||
| mux_fle_3_in_1 | 88.36 | 88.36 | ||
| mux_fle_3_in_2 | 88.36 | 88.36 | ||
| mux_fle_3_in_3 | 83.02 | 83.02 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 82.08 | 82.08 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.04 | 89.04 | ||
| mux_fle_4_in_1 | 89.04 | 89.04 | ||
| mux_fle_4_in_2 | 89.73 | 89.73 | ||
| mux_fle_4_in_3 | 84.91 | 84.91 | ||
| mux_fle_4_in_4 | 83.96 | 83.96 | ||
| mux_fle_4_in_5 | 83.02 | 83.02 | ||
| mux_fle_5_clk_0 | 67.65 | 67.65 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 89.73 | 89.73 | ||
| mux_fle_5_in_2 | 90.41 | 90.41 | ||
| mux_fle_5_in_3 | 82.08 | 82.08 | ||
| mux_fle_5_in_4 | 83.02 | 83.02 | ||
| mux_fle_5_in_5 | 72.64 | 72.64 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 88.36 | 88.36 | ||
| mux_fle_6_in_1 | 89.04 | 89.04 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.96 | 83.96 | ||
| mux_fle_6_in_4 | 82.08 | 82.08 | ||
| mux_fle_6_in_5 | 81.13 | 81.13 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 89.73 | 89.73 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 82.08 | 82.08 | ||
| mux_fle_8_clk_0 | 67.65 | 67.65 | ||
| mux_fle_8_in_0 | 87.67 | 87.67 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 87.67 | 87.67 | ||
| mux_fle_8_in_3 | 81.13 | 81.13 | ||
| mux_fle_8_in_4 | 82.08 | 82.08 | ||
| mux_fle_8_in_5 | 82.08 | 82.08 | ||
| mux_fle_9_clk_0 | 70.59 | 70.59 | ||
| mux_fle_9_in_0 | 86.99 | 86.99 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.04 | 89.04 | ||
| mux_fle_9_in_3 | 82.08 | 82.08 | ||
| mux_fle_9_in_4 | 81.13 | 81.13 | ||
| mux_fle_9_in_5 | 80.19 | 80.19 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.87 | 64.87 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.38 | 100.00 | 70.14 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_12__3_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.64 | 100.00 | 67.93 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.15 | 100.00 | 69.45 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 82.81 | 100.00 | 68.43 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 83.16 | 100.00 | 69.47 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.06 | 100.00 | 69.19 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 83.39 | 100.00 | 70.17 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.36 | 100.00 | 70.07 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.27 | 100.00 | 69.81 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.21 | 100.00 | 69.63 | 80.00 |
| mem_fle_0_cin_0 | 81.72 | 100.00 | 65.15 | 80.00 |
| mem_fle_0_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_0_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_0_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_1_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_2_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_3_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_1 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_4_in_2 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_4_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_6_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_4 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_6_in_5 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_7_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_7_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_7_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_8_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_8_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_9_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_9_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 50.00 | 50.00 | ||
| mux_fle_0_clk_0 | 70.59 | 70.59 | ||
| mux_fle_0_in_0 | 90.41 | 90.41 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 86.79 | 86.79 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 75.47 | 75.47 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 88.36 | 88.36 | ||
| mux_fle_1_in_1 | 90.41 | 90.41 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 83.96 | 83.96 | ||
| mux_fle_1_in_4 | 81.13 | 81.13 | ||
| mux_fle_1_in_5 | 83.02 | 83.02 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 89.73 | 89.73 | ||
| mux_fle_2_in_1 | 89.73 | 89.73 | ||
| mux_fle_2_in_2 | 87.67 | 87.67 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 81.13 | 81.13 | ||
| mux_fle_2_in_5 | 80.19 | 80.19 | ||
| mux_fle_3_clk_0 | 67.65 | 67.65 | ||
| mux_fle_3_in_0 | 89.73 | 89.73 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 85.85 | 85.85 | ||
| mux_fle_3_in_4 | 85.85 | 85.85 | ||
| mux_fle_3_in_5 | 74.53 | 74.53 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 88.36 | 88.36 | ||
| mux_fle_4_in_1 | 88.36 | 88.36 | ||
| mux_fle_4_in_2 | 87.67 | 87.67 | ||
| mux_fle_4_in_3 | 85.85 | 85.85 | ||
| mux_fle_4_in_4 | 82.08 | 82.08 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 89.73 | 89.73 | ||
| mux_fle_5_in_1 | 90.41 | 90.41 | ||
| mux_fle_5_in_2 | 87.67 | 87.67 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 82.08 | 82.08 | ||
| mux_fle_5_in_5 | 82.08 | 82.08 | ||
| mux_fle_6_clk_0 | 67.65 | 67.65 | ||
| mux_fle_6_in_0 | 86.99 | 86.99 | ||
| mux_fle_6_in_1 | 88.36 | 88.36 | ||
| mux_fle_6_in_2 | 89.73 | 89.73 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 82.08 | 82.08 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 70.59 | 70.59 | ||
| mux_fle_7_in_0 | 88.36 | 88.36 | ||
| mux_fle_7_in_1 | 86.99 | 86.99 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 85.85 | 85.85 | ||
| mux_fle_7_in_4 | 84.91 | 84.91 | ||
| mux_fle_7_in_5 | 86.79 | 86.79 | ||
| mux_fle_8_clk_0 | 70.59 | 70.59 | ||
| mux_fle_8_in_0 | 88.36 | 88.36 | ||
| mux_fle_8_in_1 | 89.73 | 89.73 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 83.02 | 83.02 | ||
| mux_fle_8_in_4 | 86.79 | 86.79 | ||
| mux_fle_8_in_5 | 83.02 | 83.02 | ||
| mux_fle_9_clk_0 | 64.71 | 64.71 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 90.41 | 90.41 | ||
| mux_fle_9_in_2 | 88.36 | 88.36 | ||
| mux_fle_9_in_3 | 86.79 | 86.79 | ||
| mux_fle_9_in_4 | 83.96 | 83.96 | ||
| mux_fle_9_in_5 | 83.02 | 83.02 |
| SCORE | LINE | TOGGLE | BRANCH |
| 64.93 | 64.93 |
| SCORE | LINE | TOGGLE | BRANCH |
| 83.40 | 100.00 | 70.21 | 80.00 |
| SCORE | LINE | TOGGLE | BRANCH | NAME |
| 81.62 | 81.62 | grid_clb_12__4_ |
| NAME | SCORE | LINE | TOGGLE | BRANCH |
| direct_interc_0_ | 100.00 | 100.00 | ||
| direct_interc_100_ | 100.00 | 100.00 | ||
| direct_interc_101_ | 100.00 | 100.00 | ||
| direct_interc_10_ | 100.00 | 100.00 | ||
| direct_interc_11_ | 100.00 | 100.00 | ||
| direct_interc_12_ | 100.00 | 100.00 | ||
| direct_interc_13_ | 100.00 | 100.00 | ||
| direct_interc_14_ | 100.00 | 100.00 | ||
| direct_interc_15_ | 100.00 | 100.00 | ||
| direct_interc_16_ | 100.00 | 100.00 | ||
| direct_interc_17_ | 100.00 | 100.00 | ||
| direct_interc_18_ | 100.00 | 100.00 | ||
| direct_interc_19_ | 100.00 | 100.00 | ||
| direct_interc_1_ | 100.00 | 100.00 | ||
| direct_interc_20_ | 100.00 | 100.00 | ||
| direct_interc_21_ | 100.00 | 100.00 | ||
| direct_interc_22_ | 100.00 | 100.00 | ||
| direct_interc_23_ | 0.00 | 0.00 | ||
| direct_interc_24_ | 100.00 | 100.00 | ||
| direct_interc_25_ | 100.00 | 100.00 | ||
| direct_interc_26_ | 100.00 | 100.00 | ||
| direct_interc_27_ | 100.00 | 100.00 | ||
| direct_interc_28_ | 100.00 | 100.00 | ||
| direct_interc_29_ | 100.00 | 100.00 | ||
| direct_interc_2_ | 100.00 | 100.00 | ||
| direct_interc_30_ | 100.00 | 100.00 | ||
| direct_interc_31_ | 100.00 | 100.00 | ||
| direct_interc_32_ | 100.00 | 100.00 | ||
| direct_interc_33_ | 100.00 | 100.00 | ||
| direct_interc_34_ | 100.00 | 100.00 | ||
| direct_interc_35_ | 100.00 | 100.00 | ||
| direct_interc_36_ | 100.00 | 100.00 | ||
| direct_interc_37_ | 100.00 | 100.00 | ||
| direct_interc_38_ | 100.00 | 100.00 | ||
| direct_interc_39_ | 100.00 | 100.00 | ||
| direct_interc_3_ | 100.00 | 100.00 | ||
| direct_interc_40_ | 100.00 | 100.00 | ||
| direct_interc_41_ | 100.00 | 100.00 | ||
| direct_interc_42_ | 100.00 | 100.00 | ||
| direct_interc_43_ | 100.00 | 100.00 | ||
| direct_interc_44_ | 100.00 | 100.00 | ||
| direct_interc_45_ | 100.00 | 100.00 | ||
| direct_interc_46_ | 100.00 | 100.00 | ||
| direct_interc_47_ | 100.00 | 100.00 | ||
| direct_interc_48_ | 100.00 | 100.00 | ||
| direct_interc_49_ | 100.00 | 100.00 | ||
| direct_interc_4_ | 100.00 | 100.00 | ||
| direct_interc_50_ | 100.00 | 100.00 | ||
| direct_interc_51_ | 100.00 | 100.00 | ||
| direct_interc_52_ | 100.00 | 100.00 | ||
| direct_interc_53_ | 100.00 | 100.00 | ||
| direct_interc_54_ | 100.00 | 100.00 | ||
| direct_interc_55_ | 100.00 | 100.00 | ||
| direct_interc_56_ | 100.00 | 100.00 | ||
| direct_interc_57_ | 100.00 | 100.00 | ||
| direct_interc_58_ | 100.00 | 100.00 | ||
| direct_interc_59_ | 100.00 | 100.00 | ||
| direct_interc_5_ | 100.00 | 100.00 | ||
| direct_interc_60_ | 100.00 | 100.00 | ||
| direct_interc_61_ | 100.00 | 100.00 | ||
| direct_interc_62_ | 100.00 | 100.00 | ||
| direct_interc_63_ | 100.00 | 100.00 | ||
| direct_interc_64_ | 100.00 | 100.00 | ||
| direct_interc_65_ | 100.00 | 100.00 | ||
| direct_interc_66_ | 100.00 | 100.00 | ||
| direct_interc_67_ | 100.00 | 100.00 | ||
| direct_interc_68_ | 100.00 | 100.00 | ||
| direct_interc_69_ | 100.00 | 100.00 | ||
| direct_interc_6_ | 100.00 | 100.00 | ||
| direct_interc_70_ | 100.00 | 100.00 | ||
| direct_interc_71_ | 100.00 | 100.00 | ||
| direct_interc_72_ | 100.00 | 100.00 | ||
| direct_interc_73_ | 100.00 | 100.00 | ||
| direct_interc_74_ | 100.00 | 100.00 | ||
| direct_interc_75_ | 100.00 | 100.00 | ||
| direct_interc_76_ | 100.00 | 100.00 | ||
| direct_interc_77_ | 100.00 | 100.00 | ||
| direct_interc_78_ | 100.00 | 100.00 | ||
| direct_interc_79_ | 100.00 | 100.00 | ||
| direct_interc_7_ | 100.00 | 100.00 | ||
| direct_interc_80_ | 100.00 | 100.00 | ||
| direct_interc_81_ | 100.00 | 100.00 | ||
| direct_interc_82_ | 100.00 | 100.00 | ||
| direct_interc_83_ | 100.00 | 100.00 | ||
| direct_interc_84_ | 100.00 | 100.00 | ||
| direct_interc_85_ | 100.00 | 100.00 | ||
| direct_interc_86_ | 100.00 | 100.00 | ||
| direct_interc_87_ | 100.00 | 100.00 | ||
| direct_interc_88_ | 100.00 | 100.00 | ||
| direct_interc_89_ | 100.00 | 100.00 | ||
| direct_interc_8_ | 100.00 | 100.00 | ||
| direct_interc_90_ | 100.00 | 100.00 | ||
| direct_interc_91_ | 100.00 | 100.00 | ||
| direct_interc_92_ | 100.00 | 100.00 | ||
| direct_interc_93_ | 100.00 | 100.00 | ||
| direct_interc_94_ | 100.00 | 100.00 | ||
| direct_interc_95_ | 100.00 | 100.00 | ||
| direct_interc_96_ | 100.00 | 100.00 | ||
| direct_interc_97_ | 100.00 | 100.00 | ||
| direct_interc_98_ | 100.00 | 100.00 | ||
| direct_interc_99_ | 100.00 | 100.00 | ||
| direct_interc_9_ | 100.00 | 100.00 | ||
| i_and2_x1_reset | 83.33 | 83.33 | ||
| i_inv_x1_and_rst | 100.00 | 100.00 | ||
| i_mux2_x1_reset | 75.00 | 75.00 | ||
| i_nand2_x1_and_rst | 100.00 | 100.00 | ||
| i_or2_x1_set | 66.67 | 66.67 | ||
| logical_tile_clb_mode_default__fle_0 | 82.77 | 100.00 | 68.32 | 80.00 |
| logical_tile_clb_mode_default__fle_1 | 83.56 | 100.00 | 70.68 | 80.00 |
| logical_tile_clb_mode_default__fle_2 | 83.10 | 100.00 | 69.30 | 80.00 |
| logical_tile_clb_mode_default__fle_3 | 82.98 | 100.00 | 68.94 | 80.00 |
| logical_tile_clb_mode_default__fle_4 | 83.32 | 100.00 | 69.96 | 80.00 |
| logical_tile_clb_mode_default__fle_5 | 82.86 | 100.00 | 68.57 | 80.00 |
| logical_tile_clb_mode_default__fle_6 | 83.13 | 100.00 | 69.38 | 80.00 |
| logical_tile_clb_mode_default__fle_7 | 83.00 | 100.00 | 68.99 | 80.00 |
| logical_tile_clb_mode_default__fle_8 | 83.37 | 100.00 | 70.10 | 80.00 |
| logical_tile_clb_mode_default__fle_9 | 83.24 | 100.00 | 69.73 | 80.00 |
| mem_fle_0_cin_0 | 83.23 | 100.00 | 69.70 | 80.00 |
| mem_fle_0_clk_0 | 81.09 | 100.00 | 63.27 | 80.00 |
| mem_fle_0_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_0_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_0_in_5 | 79.34 | 100.00 | 58.02 | 80.00 |
| mem_fle_1_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_1_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_1 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_1_in_2 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_1_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_1_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_1_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_2_in_0 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_2_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_2_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_2_in_5 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_3_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_3_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_3_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_3_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_3_in_5 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_4_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_4_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_4_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_4_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_4 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_4_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_5_in_0 | 81.19 | 100.00 | 63.58 | 80.00 |
| mem_fle_5_in_1 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_5_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_5_in_4 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_5_in_5 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_clk_0 | 83.13 | 100.00 | 69.39 | 80.00 |
| mem_fle_6_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_6_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_6_in_2 | 79.96 | 100.00 | 59.88 | 80.00 |
| mem_fle_6_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_6_in_4 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_6_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_7_in_0 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_7_in_1 | 80.58 | 100.00 | 61.73 | 80.00 |
| mem_fle_7_in_2 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_3 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_7_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_7_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_clk_0 | 80.07 | 100.00 | 60.20 | 80.00 |
| mem_fle_8_in_0 | 81.81 | 100.00 | 65.43 | 80.00 |
| mem_fle_8_in_1 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_2 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_3 | 83.05 | 100.00 | 69.14 | 80.00 |
| mem_fle_8_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_8_in_5 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_clk_0 | 82.11 | 100.00 | 66.33 | 80.00 |
| mem_fle_9_in_0 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_1 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_2 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_3 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_4 | 82.43 | 100.00 | 67.28 | 80.00 |
| mem_fle_9_in_5 | 83.05 | 100.00 | 69.14 | 80.00 |
| mux_fle_0_cin_0 | 54.55 | 54.55 | ||
| mux_fle_0_clk_0 | 64.71 | 64.71 | ||
| mux_fle_0_in_0 | 89.04 | 89.04 | ||
| mux_fle_0_in_1 | 89.04 | 89.04 | ||
| mux_fle_0_in_2 | 88.36 | 88.36 | ||
| mux_fle_0_in_3 | 85.85 | 85.85 | ||
| mux_fle_0_in_4 | 85.85 | 85.85 | ||
| mux_fle_0_in_5 | 71.70 | 71.70 | ||
| mux_fle_1_clk_0 | 70.59 | 70.59 | ||
| mux_fle_1_in_0 | 89.73 | 89.73 | ||
| mux_fle_1_in_1 | 86.99 | 86.99 | ||
| mux_fle_1_in_2 | 88.36 | 88.36 | ||
| mux_fle_1_in_3 | 86.79 | 86.79 | ||
| mux_fle_1_in_4 | 83.96 | 83.96 | ||
| mux_fle_1_in_5 | 83.96 | 83.96 | ||
| mux_fle_2_clk_0 | 70.59 | 70.59 | ||
| mux_fle_2_in_0 | 86.30 | 86.30 | ||
| mux_fle_2_in_1 | 90.41 | 90.41 | ||
| mux_fle_2_in_2 | 89.04 | 89.04 | ||
| mux_fle_2_in_3 | 84.91 | 84.91 | ||
| mux_fle_2_in_4 | 86.79 | 86.79 | ||
| mux_fle_2_in_5 | 76.42 | 76.42 | ||
| mux_fle_3_clk_0 | 70.59 | 70.59 | ||
| mux_fle_3_in_0 | 89.04 | 89.04 | ||
| mux_fle_3_in_1 | 89.73 | 89.73 | ||
| mux_fle_3_in_2 | 90.41 | 90.41 | ||
| mux_fle_3_in_3 | 86.79 | 86.79 | ||
| mux_fle_3_in_4 | 84.91 | 84.91 | ||
| mux_fle_3_in_5 | 72.64 | 72.64 | ||
| mux_fle_4_clk_0 | 67.65 | 67.65 | ||
| mux_fle_4_in_0 | 89.73 | 89.73 | ||
| mux_fle_4_in_1 | 90.41 | 90.41 | ||
| mux_fle_4_in_2 | 89.04 | 89.04 | ||
| mux_fle_4_in_3 | 83.02 | 83.02 | ||
| mux_fle_4_in_4 | 83.02 | 83.02 | ||
| mux_fle_4_in_5 | 85.85 | 85.85 | ||
| mux_fle_5_clk_0 | 70.59 | 70.59 | ||
| mux_fle_5_in_0 | 88.36 | 88.36 | ||
| mux_fle_5_in_1 | 88.36 | 88.36 | ||
| mux_fle_5_in_2 | 89.73 | 89.73 | ||
| mux_fle_5_in_3 | 85.85 | 85.85 | ||
| mux_fle_5_in_4 | 86.79 | 86.79 | ||
| mux_fle_5_in_5 | 84.91 | 84.91 | ||
| mux_fle_6_clk_0 | 70.59 | 70.59 | ||
| mux_fle_6_in_0 | 89.73 | 89.73 | ||
| mux_fle_6_in_1 | 90.41 | 90.41 | ||
| mux_fle_6_in_2 | 86.99 | 86.99 | ||
| mux_fle_6_in_3 | 83.02 | 83.02 | ||
| mux_fle_6_in_4 | 81.13 | 81.13 | ||
| mux_fle_6_in_5 | 83.96 | 83.96 | ||
| mux_fle_7_clk_0 | 67.65 | 67.65 | ||
| mux_fle_7_in_0 | 90.41 | 90.41 | ||
| mux_fle_7_in_1 | 87.67 | 87.67 | ||
| mux_fle_7_in_2 | 89.04 | 89.04 | ||
| mux_fle_7_in_3 | 84.91 | 84.91 | ||
| mux_fle_7_in_4 | 83.96 | 83.96 | ||
| mux_fle_7_in_5 | 85.85 | 85.85 | ||
| mux_fle_8_clk_0 | 61.76 | 61.76 | ||
| mux_fle_8_in_0 | 89.04 | 89.04 | ||
| mux_fle_8_in_1 | 90.41 | 90.41 | ||
| mux_fle_8_in_2 | 90.41 | 90.41 | ||
| mux_fle_8_in_3 | 86.79 | 86.79 | ||
| mux_fle_8_in_4 | 83.96 | 83.96 | ||
| mux_fle_8_in_5 | 84.91 | 84.91 | ||
| mux_fle_9_clk_0 | 67.65 | 67.65 | ||
| mux_fle_9_in_0 | 89.73 | 89.73 | ||
| mux_fle_9_in_1 | 89.73 | 89.73 | ||
| mux_fle_9_in_2 | 89.73 | 89.73 | ||
| mux_fle_9_in_3 | 85.85 | 85.85 | ||
| mux_fle_9_in_4 | 83.02 | 83.02 | ||
| mux_fle_9_in_5 | 86.79 | 86.79 |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 245 | 67.12 |
| Total Bits | 8576 | 5600 | 65.30 |
| Total Bits 0->1 | 4288 | 2838 | 66.18 |
| Total Bits 1->0 | 4288 | 2762 | 64.41 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 223 | 66.17 |
| Signal Bits | 1738 | 995 | 57.25 |
| Signal Bits 0->1 | 869 | 535 | 61.57 |
| Signal Bits 1->0 | 869 | 460 | 52.93 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:1] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1:3] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:2] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | No | No | Yes |
| mux_tree_size20_17_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | No | No | Yes |
| mux_tree_size20_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | No | Yes |
| mux_tree_size20_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:1] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1] | No | No | Yes |
| mux_tree_size20_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | Yes |
| mux_tree_size20_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | No | No | Yes |
| mux_tree_size20_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | No | Yes |
| mux_tree_size20_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[1] | No | No | Yes |
| mux_tree_size20_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | No | No | Yes |
| mux_tree_size20_6_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0:1] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:1] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0:1] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:2] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:2] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[2] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | No | No | Yes |
| mux_tree_size30_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0:1] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[1:3] | No | No | Yes |
| mux_tree_size30_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1:2] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[2] | No | No | Yes |
| mux_tree_size30_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0:1] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 241 | 66.03 |
| Total Bits | 8576 | 5589 | 65.17 |
| Total Bits 0->1 | 4288 | 2838 | 66.18 |
| Total Bits 1->0 | 4288 | 2751 | 64.16 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 219 | 64.99 |
| Signal Bits | 1738 | 984 | 56.62 |
| Signal Bits 0->1 | 869 | 535 | 61.57 |
| Signal Bits 1->0 | 869 | 449 | 51.67 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[2] | No | No | Yes |
| mux_tree_size20_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0:1] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:2] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0:1] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0:1] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1:2] | No | No | Yes |
| mux_tree_size20_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0:2] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | No | No | Yes |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | No | No | Yes |
| mux_tree_size20_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[2] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1:2] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[2] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[2] | No | No | Yes |
| mux_tree_size30_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0:2] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:3] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[1] | No | No | Yes |
| mux_tree_size30_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | No | No | Yes |
| mux_tree_size30_22_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:2] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[3] | No | No | Yes |
| mux_tree_size30_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2:3] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0:1] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[2] | No | No | Yes |
| mux_tree_size30_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | No | No | Yes |
| mux_tree_size30_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | No | No | Yes |
| mux_tree_size4_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 237 | 64.93 |
| Total Bits | 8576 | 5587 | 65.15 |
| Total Bits 0->1 | 4288 | 2836 | 66.14 |
| Total Bits 1->0 | 4288 | 2751 | 64.16 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 215 | 63.80 |
| Signal Bits | 1738 | 982 | 56.50 |
| Signal Bits 0->1 | 869 | 533 | 61.33 |
| Signal Bits 1->0 | 869 | 449 | 51.67 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:1] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | No | Yes |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[3] | No | No | Yes |
| mux_tree_size20_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2:3] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[2] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:2] | No | No | Yes |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1] | No | No | Yes |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[1:2] | No | No | Yes |
| mux_tree_size20_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[3] | No | No | No |
| mux_tree_size20_5_sram[2] | No | No | Yes |
| mux_tree_size20_5_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[2] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:2] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | No | No | Yes |
| mux_tree_size30_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[1] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | No | No | Yes |
| mux_tree_size30_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[3] | No | No | Yes |
| mux_tree_size30_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | No | No | Yes |
| mux_tree_size30_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | No | No | Yes |
| mux_tree_size30_28_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | No | No | Yes |
| mux_tree_size30_29_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[1:4] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[2:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0:1] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[1] | No | No | Yes |
| mux_tree_size4_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 237 | 64.93 |
| Total Bits | 8576 | 5583 | 65.10 |
| Total Bits 0->1 | 4288 | 2836 | 66.14 |
| Total Bits 1->0 | 4288 | 2747 | 64.06 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 215 | 63.80 |
| Signal Bits | 1738 | 978 | 56.27 |
| Signal Bits 0->1 | 869 | 533 | 61.33 |
| Signal Bits 1->0 | 869 | 445 | 51.21 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[2] | No | No | Yes |
| mux_tree_size20_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | No | No | Yes |
| mux_tree_size20_12_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | No | Yes |
| mux_tree_size20_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1:2] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | No | Yes |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[3] | No | No | Yes |
| mux_tree_size20_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[1:4] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[2:3] | No | No | Yes |
| mux_tree_size20_20_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:3] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[3] | No | No | Yes |
| mux_tree_size20_28_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:3] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[2:3] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | No | No | Yes |
| mux_tree_size20_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:1] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | No | No | Yes |
| mux_tree_size30_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:2] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | No | No | Yes |
| mux_tree_size30_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | No | No | Yes |
| mux_tree_size30_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | No | No | Yes |
| mux_tree_size30_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[2:3] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[1] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2:3] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | No | No | Yes |
| mux_tree_size30_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[3] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1:3] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2:3] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[1] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 231 | 63.29 |
| Total Bits | 8576 | 5561 | 64.84 |
| Total Bits 0->1 | 4288 | 2827 | 65.93 |
| Total Bits 1->0 | 4288 | 2734 | 63.76 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 210 | 62.31 |
| Signal Bits | 1738 | 958 | 55.12 |
| Signal Bits 0->1 | 869 | 525 | 60.41 |
| Signal Bits 1->0 | 869 | 433 | 49.83 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1:3] | No | No | Yes |
| mux_tree_size20_14_sram[0] | No | No | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2:3] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0:3] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[2] | No | No | Yes |
| mux_tree_size20_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | No | Yes |
| mux_tree_size20_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:2] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[3] | No | No | Yes |
| mux_tree_size20_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0:1] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0:1] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | No | No | Yes |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | No | Yes |
| mux_tree_size20_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:3] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0:2] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[3] | No | No | Yes |
| mux_tree_size30_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[1] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[1] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[1:3] | No | No | Yes |
| mux_tree_size30_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | No | No | Yes |
| mux_tree_size30_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0:3] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:1] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | No | No | Yes |
| mux_tree_size30_3_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[1] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0:1] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[3] | No | No | Yes |
| mux_tree_size30_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | No | No | Yes |
| mux_tree_size30_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0:1] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 212 | 58.08 |
| Total Bits | 8576 | 5538 | 64.58 |
| Total Bits 0->1 | 4288 | 2814 | 65.62 |
| Total Bits 1->0 | 4288 | 2724 | 63.53 |
| Ports | 28 | 20 | 71.43 |
| Port Bits | 6838 | 4601 | 67.29 |
| Port Bits 0->1 | 3419 | 2301 | 67.30 |
| Port Bits 1->0 | 3419 | 2300 | 67.27 |
| Signals | 337 | 192 | 56.97 |
| Signal Bits | 1738 | 937 | 53.91 |
| Signal Bits 0->1 | 869 | 513 | 59.03 |
| Signal Bits 1->0 | 869 | 424 | 48.79 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | No | No | No | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | No | No | Yes |
| mux_tree_size20_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1:3] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[3] | No | No | Yes |
| mux_tree_size20_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[1] | No | No | Yes |
| mux_tree_size20_19_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | No | No | Yes |
| mux_tree_size20_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | No | No | Yes |
| mux_tree_size20_20_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0:1] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1:3] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:2] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | No | No | Yes |
| mux_tree_size20_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0:1] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[1] | No | No | Yes |
| mux_tree_size30_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[3] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:3] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | No | No | Yes |
| mux_tree_size30_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[3:4] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[3] | No | No | Yes |
| mux_tree_size30_20_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | No | No | Yes |
| mux_tree_size30_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:3] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | No | No | Yes |
| mux_tree_size30_25_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[1:3] | No | No | Yes |
| mux_tree_size30_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | No | No | Yes |
| mux_tree_size30_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[2:4] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0:1] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | No | No | Yes |
| mux_tree_size4_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | No | No | No |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | No | No | No |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | No | No | No |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | No | No | No |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | No | No | No |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | No | No | No |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | No | No | No |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | No | No | No |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | No | No | No |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | No | No | No |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | No | No | No |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 229 | 62.74 |
| Total Bits | 8576 | 5556 | 64.79 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2732 | 63.71 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 208 | 61.72 |
| Signal Bits | 1738 | 953 | 54.83 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 431 | 49.60 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | Yes | No |
| mux_tree_size20_11_sram[1:2] | No | No | Yes |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0:1] | No | No | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[3] | No | No | Yes |
| mux_tree_size20_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | No | Yes |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0:2] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | Yes | No |
| mux_tree_size20_26_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0:2] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | No | No | Yes |
| mux_tree_size20_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:2] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:1] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:3] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:2] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[1] | No | No | Yes |
| mux_tree_size30_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[2] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:2] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | No | No | Yes |
| mux_tree_size30_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[2:4] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | No | No | Yes |
| mux_tree_size30_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0:1] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0:2] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0:2] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0:3] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[1] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0:1] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | Yes | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 240 | 65.75 |
| Total Bits | 8576 | 5599 | 65.29 |
| Total Bits 0->1 | 4288 | 2835 | 66.11 |
| Total Bits 1->0 | 4288 | 2764 | 64.46 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 218 | 64.69 |
| Signal Bits | 1738 | 994 | 57.19 |
| Signal Bits 0->1 | 869 | 532 | 61.22 |
| Signal Bits 1->0 | 869 | 462 | 53.16 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3] | No | No | Yes |
| mux_tree_size20_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1:2] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0:2] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | No | No | Yes |
| mux_tree_size20_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2:3] | No | No | Yes |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[2] | No | No | Yes |
| mux_tree_size20_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | No | No | Yes |
| mux_tree_size20_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[3] | No | No | Yes |
| mux_tree_size20_29_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1] | No | Yes | No |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[2] | No | No | Yes |
| mux_tree_size20_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | No | Yes |
| mux_tree_size20_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | Yes | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[2] | No | No | Yes |
| mux_tree_size30_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[1:2] | No | No | Yes |
| mux_tree_size30_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[3] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | No | No | Yes |
| mux_tree_size30_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[3] | No | No | Yes |
| mux_tree_size30_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[2] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | No | No | Yes |
| mux_tree_size30_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[3] | No | No | Yes |
| mux_tree_size30_23_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0:1] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[1:2] | No | No | Yes |
| mux_tree_size30_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0:2] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | No | No | Yes |
| mux_tree_size30_29_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[1:2] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:1] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[3] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[3] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | No | No | Yes |
| mux_tree_size4_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 231 | 63.29 |
| Total Bits | 8576 | 5586 | 65.14 |
| Total Bits 0->1 | 4288 | 2823 | 65.83 |
| Total Bits 1->0 | 4288 | 2763 | 64.44 |
| Ports | 28 | 20 | 71.43 |
| Port Bits | 6838 | 4602 | 67.30 |
| Port Bits 0->1 | 3419 | 2301 | 67.30 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 211 | 62.61 |
| Signal Bits | 1738 | 984 | 56.62 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 462 | 53.16 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | Yes | Yes | Yes | INPUT |
| clb_I3[8] | No | Yes | No | INPUT |
| clb_I3[0:7] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | Yes | No |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[3] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2:3] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | No | Yes |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[2] | No | No | Yes |
| mux_tree_size20_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | No | No | Yes |
| mux_tree_size20_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | No | No | Yes |
| mux_tree_size20_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[1:3] | No | No | Yes |
| mux_tree_size20_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0:3] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[2] | No | No | Yes |
| mux_tree_size20_5_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[2] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | No | No | Yes |
| mux_tree_size30_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[3] | No | No | Yes |
| mux_tree_size30_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[1] | No | No | Yes |
| mux_tree_size30_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[2] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2:3] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | No | No | Yes |
| mux_tree_size30_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0:1] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0:1] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[0] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 222 | 60.82 |
| Total Bits | 8576 | 5546 | 64.67 |
| Total Bits 0->1 | 4288 | 2805 | 65.42 |
| Total Bits 1->0 | 4288 | 2741 | 63.92 |
| Ports | 28 | 19 | 67.86 |
| Port Bits | 6838 | 4599 | 67.26 |
| Port Bits 0->1 | 3419 | 2299 | 67.24 |
| Port Bits 1->0 | 3419 | 2300 | 67.27 |
| Signals | 337 | 203 | 60.24 |
| Signal Bits | 1738 | 947 | 54.49 |
| Signal Bits 0->1 | 869 | 506 | 58.23 |
| Signal Bits 1->0 | 869 | 441 | 50.75 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | Yes | Yes | Yes | INPUT |
| clb_I3[7:8] | No | Yes | No | INPUT |
| clb_I3[0:6] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | No | No | No | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[3] | No | No | Yes |
| mux_tree_size20_10_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[0:4] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:2] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | No | Yes |
| mux_tree_size20_14_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2:3] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1:2] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0:3] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | No | Yes | No |
| mux_tree_size20_23_sram[2] | No | No | Yes |
| mux_tree_size20_23_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0:1] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | No | Yes |
| mux_tree_size20_26_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0:3] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[1] | No | No | Yes |
| mux_tree_size20_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | Yes | No |
| mux_tree_size20_5_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[1] | No | No | Yes |
| mux_tree_size20_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | Yes | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:3] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0:1] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | No | No | Yes |
| mux_tree_size30_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | No | No | Yes |
| mux_tree_size30_16_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[1] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0:3] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | No | No | Yes |
| mux_tree_size30_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[2:4] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:2] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | No | No | Yes |
| mux_tree_size30_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[1] | No | No | Yes |
| mux_tree_size30_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:2] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | No | No | Yes |
| mux_tree_size30_3_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[1] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | No | No | Yes |
| mux_tree_size30_5_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[3] | No | No | Yes |
| mux_tree_size30_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[1] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[1] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | No | No | Yes |
| mux_tree_size4_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | No | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 235 | 64.38 |
| Total Bits | 8576 | 5574 | 65.00 |
| Total Bits 0->1 | 4288 | 2817 | 65.69 |
| Total Bits 1->0 | 4288 | 2757 | 64.30 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 213 | 63.20 |
| Signal Bits | 1738 | 969 | 55.75 |
| Signal Bits 0->1 | 869 | 514 | 59.15 |
| Signal Bits 1->0 | 869 | 455 | 52.36 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:1] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | Yes | No |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[2] | No | Yes | No |
| mux_tree_size20_14_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[3] | No | No | Yes |
| mux_tree_size20_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[1] | No | No | Yes |
| mux_tree_size20_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[1:3] | No | No | Yes |
| mux_tree_size20_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[1] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | Yes | No |
| mux_tree_size20_26_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | No |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | No | No |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[2] | No | Yes | No |
| mux_tree_size20_2_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[2:3] | No | No | No |
| mux_tree_size20_5_sram[1] | No | No | Yes |
| mux_tree_size20_5_sram[0] | No | No | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0:1] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[1] | No | No | Yes |
| mux_tree_size20_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | Yes | No |
| mux_tree_size20_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | No | No | Yes |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[1] | No | No | Yes |
| mux_tree_size30_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0:1] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[3] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[2] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0:3] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0:2] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1:2] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0:1] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[1] | No | No | Yes |
| mux_tree_size30_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[1] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[1] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | No | No | Yes |
| mux_tree_size4_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | Yes | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | Yes | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 239 | 65.48 |
| Total Bits | 8576 | 5599 | 65.29 |
| Total Bits 0->1 | 4288 | 2835 | 66.11 |
| Total Bits 1->0 | 4288 | 2764 | 64.46 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 217 | 64.39 |
| Signal Bits | 1738 | 994 | 57.19 |
| Signal Bits 0->1 | 869 | 532 | 61.22 |
| Signal Bits 1->0 | 869 | 462 | 53.16 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | No | No | Yes |
| mux_tree_size20_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | No | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2:3] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0:3] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[3] | No | Yes | No |
| mux_tree_size20_23_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[2] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | No | No | Yes |
| mux_tree_size20_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | No | No | Yes |
| mux_tree_size20_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[1] | No | No | Yes |
| mux_tree_size20_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram[0] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[3] | No | No | Yes |
| mux_tree_size30_12_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[1:2] | No | No | Yes |
| mux_tree_size30_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[3] | No | No | Yes |
| mux_tree_size30_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[1:4] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[2] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[3:4] | No | No | Yes |
| mux_tree_size30_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[3] | No | No | Yes |
| mux_tree_size30_28_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2:3] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1:3] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[3] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[1] | No | No | Yes |
| mux_tree_size4_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | No | No | Yes |
| mux_tree_size4_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 245 | 67.12 |
| Total Bits | 8576 | 5608 | 65.39 |
| Total Bits 0->1 | 4288 | 2838 | 66.18 |
| Total Bits 1->0 | 4288 | 2770 | 64.60 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 223 | 66.17 |
| Signal Bits | 1738 | 1003 | 57.71 |
| Signal Bits 0->1 | 869 | 535 | 61.57 |
| Signal Bits 1->0 | 869 | 468 | 53.86 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0:1] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[3] | No | No | Yes |
| mux_tree_size20_25_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:2] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | No | No | Yes |
| mux_tree_size20_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | No | No | Yes |
| mux_tree_size20_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0:2] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | No | No | Yes |
| mux_tree_size30_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[2] | No | No | Yes |
| mux_tree_size30_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[3] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | No | No | Yes |
| mux_tree_size30_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[1] | No | No | Yes |
| mux_tree_size30_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:2] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0:1] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | No | No | Yes |
| mux_tree_size30_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | No | No | Yes |
| mux_tree_size30_29_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[0] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 236 | 64.66 |
| Total Bits | 8576 | 5570 | 64.95 |
| Total Bits 0->1 | 4288 | 2832 | 66.04 |
| Total Bits 1->0 | 4288 | 2738 | 63.85 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 214 | 63.50 |
| Signal Bits | 1738 | 965 | 55.52 |
| Signal Bits 0->1 | 869 | 529 | 60.87 |
| Signal Bits 1->0 | 869 | 436 | 50.17 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0:1] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1] | No | No | Yes |
| mux_tree_size20_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[2:3] | No | No | Yes |
| mux_tree_size20_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | Yes | No |
| mux_tree_size20_20_sram[1:3] | No | No | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | No | No | Yes |
| mux_tree_size20_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | No | No | Yes |
| mux_tree_size20_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | Yes | No |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | No | No | Yes |
| mux_tree_size20_25_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | Yes |
| mux_tree_size20_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[2] | No | No | Yes |
| mux_tree_size20_29_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | Yes | No |
| mux_tree_size20_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1:2] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[3] | No | No | Yes |
| mux_tree_size30_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:2] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[2:4] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0:1] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | No | No | Yes |
| mux_tree_size30_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:2] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[3:4] | No | No | Yes |
| mux_tree_size30_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0:1] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0:2] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[2] | No | No | Yes |
| mux_tree_size30_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2:3] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | No | No | Yes |
| mux_tree_size4_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 244 | 66.85 |
| Total Bits | 8576 | 5612 | 65.44 |
| Total Bits 0->1 | 4288 | 2833 | 66.07 |
| Total Bits 1->0 | 4288 | 2779 | 64.81 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 222 | 65.88 |
| Signal Bits | 1738 | 1007 | 57.94 |
| Signal Bits 0->1 | 869 | 530 | 60.99 |
| Signal Bits 1->0 | 869 | 477 | 54.89 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | No | Yes |
| mux_tree_size20_11_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0:2] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | No | No | Yes |
| mux_tree_size20_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[2] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0:1] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0:1] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | No | No | Yes |
| mux_tree_size20_20_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | No | No | Yes |
| mux_tree_size20_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[3] | No | No | Yes |
| mux_tree_size20_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[2] | No | No | Yes |
| mux_tree_size20_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[2:3] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:1] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram[0] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[2] | No | No | Yes |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[2:3] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[1:4] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[2:3] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | No | No | Yes |
| mux_tree_size30_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[3] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:1] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[3] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[3] | No | No | Yes |
| mux_tree_size30_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0:2] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[1] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[1] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | No | No | Yes |
| mux_tree_size4_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 230 | 63.01 |
| Total Bits | 8576 | 5569 | 64.94 |
| Total Bits 0->1 | 4288 | 2826 | 65.90 |
| Total Bits 1->0 | 4288 | 2743 | 63.97 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 209 | 62.02 |
| Signal Bits | 1738 | 966 | 55.58 |
| Signal Bits 0->1 | 869 | 524 | 60.30 |
| Signal Bits 1->0 | 869 | 442 | 50.86 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[2:4] | No | No | Yes |
| mux_tree_size20_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | No | No | Yes |
| mux_tree_size20_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[2] | No | No | Yes |
| mux_tree_size20_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | No | Yes |
| mux_tree_size20_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[3] | No | No | Yes |
| mux_tree_size20_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | No | No | Yes |
| mux_tree_size20_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:1] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2:3] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1:2] | No | No | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[1:3] | No | No | Yes |
| mux_tree_size20_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[1] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:3] | No | No | Yes |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1:2] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1:2] | No | No | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1:3] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[2:3] | No | No | Yes |
| mux_tree_size30_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:1] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | No | No | Yes |
| mux_tree_size30_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | No | No | Yes |
| mux_tree_size30_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[3] | No | No | Yes |
| mux_tree_size30_27_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[3] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[1] | No | No | Yes |
| mux_tree_size30_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0:1] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[1] | No | No | Yes |
| mux_tree_size4_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 235 | 64.38 |
| Total Bits | 8576 | 5584 | 65.11 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2760 | 64.37 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 214 | 63.50 |
| Signal Bits | 1738 | 981 | 56.44 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 459 | 52.82 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:2] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | No | No | Yes |
| mux_tree_size20_16_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[2:3] | No | No | Yes |
| mux_tree_size20_17_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | No | Yes |
| mux_tree_size20_20_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[3] | No | No | Yes |
| mux_tree_size20_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0:1] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | Yes |
| mux_tree_size20_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[2] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0:2] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[3] | No | No | Yes |
| mux_tree_size30_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | No | No | Yes |
| mux_tree_size30_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:2] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[2] | No | No | Yes |
| mux_tree_size30_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:1] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[3] | No | No | Yes |
| mux_tree_size30_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[3] | No | No | Yes |
| mux_tree_size30_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[2:3] | No | No | Yes |
| mux_tree_size30_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[3] | No | No | Yes |
| mux_tree_size30_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[1] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[1:4] | No | No | Yes |
| mux_tree_size30_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:2] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[3] | No | No | Yes |
| mux_tree_size30_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 224 | 61.37 |
| Total Bits | 8576 | 5563 | 64.87 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2739 | 63.88 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 203 | 60.24 |
| Signal Bits | 1738 | 960 | 55.24 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 438 | 50.40 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | No | No | Yes |
| mux_tree_size20_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:2] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:1] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1:2] | No | No | Yes |
| mux_tree_size20_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | Yes | No |
| mux_tree_size20_26_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:2] | No | Yes | No |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[3] | No | No | Yes |
| mux_tree_size20_27_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:2] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | No | No | Yes |
| mux_tree_size20_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:2] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | No | No | Yes |
| mux_tree_size20_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | No | No | Yes |
| mux_tree_size20_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[3] | No | No | Yes |
| mux_tree_size20_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:2] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1:3] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[2:3] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[2:3] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | No | No | Yes |
| mux_tree_size30_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:1] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[3] | No | No | Yes |
| mux_tree_size30_22_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[2] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | No | No | Yes |
| mux_tree_size30_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | No | No | Yes |
| mux_tree_size30_29_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0:1] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[1] | No | No | Yes |
| mux_tree_size30_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1:3] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 244 | 66.85 |
| Total Bits | 8576 | 5601 | 65.31 |
| Total Bits 0->1 | 4288 | 2835 | 66.11 |
| Total Bits 1->0 | 4288 | 2766 | 64.51 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4604 | 67.33 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 223 | 66.17 |
| Signal Bits | 1738 | 997 | 57.36 |
| Signal Bits 0->1 | 869 | 533 | 61.33 |
| Signal Bits 1->0 | 869 | 464 | 53.39 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[1:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0] | No | Yes | No | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:1] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | No | No | Yes |
| mux_tree_size20_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | No | No | Yes |
| mux_tree_size20_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[3] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1:2] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | No | No | Yes |
| mux_tree_size20_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1] | No | No | Yes |
| mux_tree_size20_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | No | No | Yes |
| mux_tree_size20_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | No | No | Yes |
| mux_tree_size20_27_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0:1] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | No | No | Yes |
| mux_tree_size20_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | No | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | Yes | No |
| mux_tree_size20_8_sram[0] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | No | No | Yes |
| mux_tree_size30_10_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[1] | No | No | Yes |
| mux_tree_size30_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[3] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[1:2] | No | No | Yes |
| mux_tree_size30_19_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[1] | No | No | Yes |
| mux_tree_size30_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[1] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:2] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2:3] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0:1] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0:1] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | No | No | Yes |
| mux_tree_size4_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 229 | 62.74 |
| Total Bits | 8576 | 5566 | 64.90 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2742 | 63.95 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 208 | 61.72 |
| Signal Bits | 1738 | 963 | 55.41 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 441 | 50.75 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:2] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[2] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | No | No | Yes |
| mux_tree_size20_13_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | No | No | Yes |
| mux_tree_size20_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[3] | No | No | Yes |
| mux_tree_size20_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[2:3] | No | No | Yes |
| mux_tree_size20_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1:3] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1] | No | No | Yes |
| mux_tree_size20_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | No | No | Yes |
| mux_tree_size20_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2:3] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[2:3] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | No | No | Yes |
| mux_tree_size20_29_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | No | Yes |
| mux_tree_size20_2_sram[1] | No | No | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[3] | No | No | Yes |
| mux_tree_size20_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0:1] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | No | No | Yes |
| mux_tree_size30_10_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | No | No | Yes |
| mux_tree_size30_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[3] | No | No | Yes |
| mux_tree_size30_15_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | No | No | Yes |
| mux_tree_size30_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0:1] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[1] | No | No | Yes |
| mux_tree_size30_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0:1] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:2] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 231 | 63.29 |
| Total Bits | 8576 | 5559 | 64.82 |
| Total Bits 0->1 | 4288 | 2826 | 65.90 |
| Total Bits 1->0 | 4288 | 2733 | 63.74 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 210 | 62.31 |
| Signal Bits | 1738 | 956 | 55.01 |
| Signal Bits 0->1 | 869 | 524 | 60.30 |
| Signal Bits 1->0 | 869 | 432 | 49.71 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:3] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2:3] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[2] | No | No | Yes |
| mux_tree_size20_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | No | No | Yes |
| mux_tree_size20_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | No | No | Yes |
| mux_tree_size20_18_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[2] | No | No | Yes |
| mux_tree_size20_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | No | No | Yes |
| mux_tree_size20_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | No | No | Yes |
| mux_tree_size20_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1:2] | No | No | Yes |
| mux_tree_size20_8_sram[0] | No | No | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | No | No | Yes |
| mux_tree_size30_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[3] | No | No | Yes |
| mux_tree_size30_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2:3] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[3] | No | No | Yes |
| mux_tree_size30_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[2] | No | No | Yes |
| mux_tree_size30_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:1] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:2] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0:1] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0:1] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[3] | No | No | Yes |
| mux_tree_size30_28_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | No | No | Yes |
| mux_tree_size30_3_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[2] | No | No | Yes |
| mux_tree_size30_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[3] | No | No | Yes |
| mux_tree_size30_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1:2] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[1] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | No | No | Yes |
| mux_tree_size4_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0:1] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | Yes | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 214 | 58.63 |
| Total Bits | 8576 | 5542 | 64.62 |
| Total Bits 0->1 | 4288 | 2802 | 65.35 |
| Total Bits 1->0 | 4288 | 2740 | 63.90 |
| Ports | 28 | 19 | 67.86 |
| Port Bits | 6838 | 4600 | 67.27 |
| Port Bits 0->1 | 3419 | 2300 | 67.27 |
| Port Bits 1->0 | 3419 | 2300 | 67.27 |
| Signals | 337 | 195 | 57.86 |
| Signal Bits | 1738 | 942 | 54.20 |
| Signal Bits 0->1 | 869 | 502 | 57.77 |
| Signal Bits 1->0 | 869 | 440 | 50.63 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[2:9] | Yes | Yes | Yes | INPUT |
| clb_I3[1] | No | Yes | No | INPUT |
| clb_I3[0] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | No | No | No | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | No | No |
| mux_tree_size20_11_sram[3] | No | Yes | No |
| mux_tree_size20_11_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:1] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[2] | No | No | Yes |
| mux_tree_size20_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | No | No |
| mux_tree_size20_14_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0:1] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:2] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | No | No |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0:1] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1:2] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[1] | No | No | Yes |
| mux_tree_size20_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1:2] | No | Yes | No |
| mux_tree_size20_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1] | No | No | Yes |
| mux_tree_size20_29_sram[0] | No | No | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | No | No |
| mux_tree_size20_2_sram[0:1] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | Yes | No |
| mux_tree_size20_5_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[2] | No | Yes | No |
| mux_tree_size20_5_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[3] | No | No | Yes |
| mux_tree_size20_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | Yes | No |
| mux_tree_size2_0_sram[0] | No | No | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:1] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[3] | No | No | Yes |
| mux_tree_size30_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[3] | No | No | Yes |
| mux_tree_size30_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[3:4] | No | No | Yes |
| mux_tree_size30_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[2] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[3] | No | No | Yes |
| mux_tree_size30_28_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[1] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0:1] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | Yes | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | Yes | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | Yes | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | Yes | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 232 | 63.56 |
| Total Bits | 8576 | 5554 | 64.76 |
| Total Bits 0->1 | 4288 | 2816 | 65.67 |
| Total Bits 1->0 | 4288 | 2738 | 63.85 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 210 | 62.31 |
| Signal Bits | 1738 | 949 | 54.60 |
| Signal Bits 0->1 | 869 | 513 | 59.03 |
| Signal Bits 1->0 | 869 | 436 | 50.17 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[3] | No | No | Yes |
| mux_tree_size20_10_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | No | Yes |
| mux_tree_size20_11_sram[1] | No | No | No |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1:2] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | No |
| mux_tree_size20_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[1:3] | No | No | Yes |
| mux_tree_size20_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | Yes | No |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0:1] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | No | No | Yes |
| mux_tree_size20_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | No | No | Yes |
| mux_tree_size20_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | No | Yes | No |
| mux_tree_size20_20_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[3] | No | No | Yes |
| mux_tree_size20_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0:1] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | No | Yes | No |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1:2] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[1:2] | No | Yes | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:1] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[1:4] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:3] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[3] | No | Yes | No |
| mux_tree_size20_8_sram[2] | No | No | Yes |
| mux_tree_size20_8_sram[0:1] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[2] | No | No | Yes |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0:1] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[2] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0:1] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | No | No | Yes |
| mux_tree_size30_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[3:4] | No | No | Yes |
| mux_tree_size30_22_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1:2] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | No | No | Yes |
| mux_tree_size30_29_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | No | No | Yes |
| mux_tree_size30_3_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[1] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[3] | No | No | Yes |
| mux_tree_size30_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | Yes | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | No | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | No | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | No | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | No | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 237 | 64.93 |
| Total Bits | 8576 | 5570 | 64.95 |
| Total Bits 0->1 | 4288 | 2818 | 65.72 |
| Total Bits 1->0 | 4288 | 2752 | 64.18 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 215 | 63.80 |
| Signal Bits | 1738 | 965 | 55.52 |
| Signal Bits 0->1 | 869 | 515 | 59.26 |
| Signal Bits 1->0 | 869 | 450 | 51.78 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1] | No | No | Yes |
| mux_tree_size20_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:3] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | Yes | No |
| mux_tree_size20_11_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | Yes | No |
| mux_tree_size20_11_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | No | No | Yes |
| mux_tree_size20_13_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:1] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | No | Yes | No |
| mux_tree_size20_14_sram[0:1] | No | No | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[2] | No | No | Yes |
| mux_tree_size20_20_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[2:3] | No | No | Yes |
| mux_tree_size20_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[1:3] | No | No | Yes |
| mux_tree_size20_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[1:2] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:2] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0:2] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[2] | No | Yes | No |
| mux_tree_size20_29_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:2] | No | Yes | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | No |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[3] | No | No | Yes |
| mux_tree_size20_8_sram[2] | No | No | No |
| mux_tree_size20_8_sram[1] | No | No | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | No | No | Yes |
| mux_tree_size20_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[2] | No | No | Yes |
| mux_tree_size30_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0:3] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[1] | No | No | Yes |
| mux_tree_size30_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[2] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | No | No | Yes |
| mux_tree_size30_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[2:3] | No | No | Yes |
| mux_tree_size30_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[2] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[2] | No | No | Yes |
| mux_tree_size30_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0:1] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | No | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | Yes | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 232 | 63.56 |
| Total Bits | 8576 | 5570 | 64.95 |
| Total Bits 0->1 | 4288 | 2820 | 65.76 |
| Total Bits 1->0 | 4288 | 2750 | 64.13 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 210 | 62.31 |
| Signal Bits | 1738 | 965 | 55.52 |
| Signal Bits 0->1 | 869 | 517 | 59.49 |
| Signal Bits 1->0 | 869 | 448 | 51.55 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1] | No | No | Yes |
| mux_tree_size20_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[3] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[1:2] | No | Yes | No |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[3] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1:3] | No | No | Yes |
| mux_tree_size20_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[1:4] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | Yes | No |
| mux_tree_size20_17_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | No | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[3] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[3] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | No | No | Yes |
| mux_tree_size20_22_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1:3] | No | Yes | No |
| mux_tree_size20_23_sram[0] | No | No | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | No | No | Yes |
| mux_tree_size20_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | No | Yes | No |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | Yes | No |
| mux_tree_size20_5_sram[3] | No | No | Yes |
| mux_tree_size20_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:1] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | Yes | No |
| mux_tree_size20_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:1] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[2:3] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[1:2] | No | No | Yes |
| mux_tree_size30_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[3] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | No | No | Yes |
| mux_tree_size30_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[2] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:3] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | No | No | Yes |
| mux_tree_size30_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[2] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[2] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | No | No | Yes |
| mux_tree_size30_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | No | No | Yes |
| mux_tree_size30_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:2] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1:3] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[1] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | No | No | Yes |
| mux_tree_size4_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[2] | No | No | Yes |
| mux_tree_size4_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | Yes | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 242 | 66.30 |
| Total Bits | 8576 | 5603 | 65.33 |
| Total Bits 0->1 | 4288 | 2836 | 66.14 |
| Total Bits 1->0 | 4288 | 2767 | 64.53 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 220 | 65.28 |
| Signal Bits | 1738 | 998 | 57.42 |
| Signal Bits 0->1 | 869 | 533 | 61.33 |
| Signal Bits 1->0 | 869 | 465 | 53.51 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[1] | No | No | Yes |
| mux_tree_size20_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1:2] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | No | No | Yes |
| mux_tree_size20_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0:2] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[2] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | Yes | No |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[3] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | Yes |
| mux_tree_size20_26_sram[2] | No | Yes | No |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2:3] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0:3] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | No | No | Yes |
| mux_tree_size20_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[1:2] | No | No | Yes |
| mux_tree_size20_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[1:2] | No | No | Yes |
| mux_tree_size30_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[1] | No | No | Yes |
| mux_tree_size30_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | No | No | Yes |
| mux_tree_size30_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[1] | No | No | Yes |
| mux_tree_size30_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[1] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[2:3] | No | No | Yes |
| mux_tree_size30_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2:3] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[1:2] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | No | No | Yes |
| mux_tree_size4_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 229 | 62.74 |
| Total Bits | 8576 | 5557 | 64.80 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2733 | 63.74 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 208 | 61.72 |
| Signal Bits | 1738 | 954 | 54.89 |
| Signal Bits 0->1 | 869 | 522 | 60.07 |
| Signal Bits 1->0 | 869 | 432 | 49.71 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:1] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[3] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[2] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[1:4] | No | No | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1:3] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[2] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[2:3] | No | No | Yes |
| mux_tree_size20_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[1:3] | No | No | Yes |
| mux_tree_size20_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[2:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0:2] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[1:4] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0:2] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1] | No | No | Yes |
| mux_tree_size20_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[2] | No | No | No |
| mux_tree_size20_2_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:1] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:3] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[2:3] | No | No | Yes |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | No | No | Yes |
| mux_tree_size30_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:1] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[2] | No | No | Yes |
| mux_tree_size30_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0:3] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[3:4] | No | No | Yes |
| mux_tree_size30_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[3] | No | No | Yes |
| mux_tree_size30_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[2:3] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0:1] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:2] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[1] | No | No | Yes |
| mux_tree_size30_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[2:3] | No | No | Yes |
| mux_tree_size30_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[3] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[3] | No | No | Yes |
| mux_tree_size30_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[1] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | No | No | Yes |
| mux_tree_size4_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 226 | 61.92 |
| Total Bits | 8576 | 5559 | 64.82 |
| Total Bits 0->1 | 4288 | 2823 | 65.83 |
| Total Bits 1->0 | 4288 | 2736 | 63.81 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 205 | 60.83 |
| Signal Bits | 1738 | 956 | 55.01 |
| Signal Bits 0->1 | 869 | 521 | 59.95 |
| Signal Bits 1->0 | 869 | 435 | 50.06 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[1:2] | No | No | Yes |
| mux_tree_size20_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1:2] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[1:4] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1:2] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[3] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[2:4] | No | No | Yes |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[3] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1:2] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[2] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0:1] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | No | No |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[1:4] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[2] | No | No | Yes |
| mux_tree_size30_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[3] | No | No | Yes |
| mux_tree_size30_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | No | No | Yes |
| mux_tree_size30_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:1] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[1:2] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0:1] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0:1] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0:3] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[1] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 230 | 63.01 |
| Total Bits | 8576 | 5559 | 64.82 |
| Total Bits 0->1 | 4288 | 2821 | 65.79 |
| Total Bits 1->0 | 4288 | 2738 | 63.85 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 209 | 62.02 |
| Signal Bits | 1738 | 956 | 55.01 |
| Signal Bits 0->1 | 869 | 519 | 59.72 |
| Signal Bits 1->0 | 869 | 437 | 50.29 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3] | No | No | Yes |
| mux_tree_size20_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | No | No | Yes |
| mux_tree_size20_10_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | No | No | Yes |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1] | No | No | No |
| mux_tree_size20_14_sram[0] | No | No | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2:3] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | No | No | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:2] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[3] | No | No | Yes |
| mux_tree_size20_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[1:2] | No | No | Yes |
| mux_tree_size20_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0:1] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | No | Yes |
| mux_tree_size20_2_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[2] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:3] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | Yes | No |
| mux_tree_size20_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0:3] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1:2] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[3] | No | No | Yes |
| mux_tree_size30_13_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0:1] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | No | No | Yes |
| mux_tree_size30_20_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0:2] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:3] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1:2] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | No | No | Yes |
| mux_tree_size30_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[2] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[1] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 231 | 63.29 |
| Total Bits | 8576 | 5577 | 65.03 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2753 | 64.20 |
| Ports | 28 | 20 | 71.43 |
| Port Bits | 6838 | 4602 | 67.30 |
| Port Bits 0->1 | 3419 | 2301 | 67.30 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 211 | 62.61 |
| Signal Bits | 1738 | 975 | 56.10 |
| Signal Bits 0->1 | 869 | 523 | 60.18 |
| Signal Bits 1->0 | 869 | 452 | 52.01 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[2:9] | Yes | Yes | Yes | INPUT |
| clb_I3[1] | No | Yes | No | INPUT |
| clb_I3[0] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:3] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:1] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2:3] | No | No | Yes |
| mux_tree_size20_11_sram[1] | No | Yes | No |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0:1] | No | No | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[3] | No | No | Yes |
| mux_tree_size20_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[2] | No | No | Yes |
| mux_tree_size20_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1:2] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[3:4] | No | No | Yes |
| mux_tree_size20_22_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[3] | No | No | Yes |
| mux_tree_size20_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[2] | No | No | Yes |
| mux_tree_size20_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[2:3] | No | No | Yes |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | No | No | Yes |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | No | No | Yes |
| mux_tree_size20_3_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:2] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | No | No | Yes |
| mux_tree_size20_6_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | Yes | No |
| mux_tree_size20_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | No | No | Yes |
| mux_tree_size30_10_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:1] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[1:4] | No | No | Yes |
| mux_tree_size30_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0:2] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0:2] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[1:3] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[3] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1:2] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[2] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[0] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[1] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | No | No | Yes |
| mux_tree_size4_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 227 | 62.19 |
| Total Bits | 8576 | 5570 | 64.95 |
| Total Bits 0->1 | 4288 | 2826 | 65.90 |
| Total Bits 1->0 | 4288 | 2744 | 63.99 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 206 | 61.13 |
| Signal Bits | 1738 | 967 | 55.64 |
| Signal Bits 0->1 | 869 | 524 | 60.30 |
| Signal Bits 1->0 | 869 | 443 | 50.98 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:1] | No | No | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | No | No | Yes |
| mux_tree_size20_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | No | No | Yes |
| mux_tree_size20_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2:3] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | No | No | Yes |
| mux_tree_size20_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[3] | No | No | Yes |
| mux_tree_size20_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0:2] | No | No | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[2:3] | No | No | Yes |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1:2] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:2] | No | No | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | No | Yes |
| mux_tree_size20_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[2:3] | No | No | Yes |
| mux_tree_size20_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:1] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1:2] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[1] | No | No | Yes |
| mux_tree_size30_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[2] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0:1] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[3] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | No | No | Yes |
| mux_tree_size30_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:1] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0:1] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0:1] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1:2] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | No | No | Yes |
| mux_tree_size30_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | No | No | Yes |
| mux_tree_size30_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[1] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | No | No | Yes |
| mux_tree_size4_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[0] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 227 | 62.19 |
| Total Bits | 8576 | 5556 | 64.79 |
| Total Bits 0->1 | 4288 | 2812 | 65.58 |
| Total Bits 1->0 | 4288 | 2744 | 63.99 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 206 | 61.13 |
| Signal Bits | 1738 | 953 | 54.83 |
| Signal Bits 0->1 | 869 | 510 | 58.69 |
| Signal Bits 1->0 | 869 | 443 | 50.98 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1:3] | No | No | Yes |
| mux_tree_size20_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | Yes | No |
| mux_tree_size20_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[3] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[1:4] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | No | No | Yes |
| mux_tree_size20_20_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:1] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[3] | No | No | Yes |
| mux_tree_size20_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2:3] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[0:4] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[2] | No | No | Yes |
| mux_tree_size20_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | No | No | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[2:3] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[3] | No | No | Yes |
| mux_tree_size30_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:2] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[2] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0:2] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[3] | No | No | Yes |
| mux_tree_size30_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[3] | No | No | Yes |
| mux_tree_size30_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0:2] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | No | No | Yes |
| mux_tree_size30_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:1] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0:1] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | No | No | Yes |
| mux_tree_size4_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 225 | 61.64 |
| Total Bits | 8576 | 5552 | 64.74 |
| Total Bits 0->1 | 4288 | 2808 | 65.49 |
| Total Bits 1->0 | 4288 | 2744 | 63.99 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 204 | 60.53 |
| Signal Bits | 1738 | 949 | 54.60 |
| Signal Bits 0->1 | 869 | 506 | 58.23 |
| Signal Bits 1->0 | 869 | 443 | 50.98 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1:2] | No | No | Yes |
| mux_tree_size20_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | No | No | Yes |
| mux_tree_size20_11_sram[0:2] | No | No | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:1] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | Yes | No |
| mux_tree_size20_14_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[3:4] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0:1] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | No | No | Yes |
| mux_tree_size20_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:1] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | No |
| mux_tree_size20_23_sram[0:3] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | No | No | Yes |
| mux_tree_size20_29_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | Yes | No |
| mux_tree_size20_2_sram[3] | No | No | Yes |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[2] | No | No | Yes |
| mux_tree_size20_5_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | Yes | No |
| mux_tree_size20_8_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | No | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2:3] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram[0] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[1:4] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[3] | No | No | Yes |
| mux_tree_size30_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0:1] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[1:3] | No | No | Yes |
| mux_tree_size30_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[2] | No | No | Yes |
| mux_tree_size30_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0:3] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0:3] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[2:3] | No | No | Yes |
| mux_tree_size30_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0:1] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2:3] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[3] | No | No | Yes |
| mux_tree_size30_29_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | No | No | Yes |
| mux_tree_size30_3_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[0] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[1] | No | No | Yes |
| mux_tree_size4_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | Yes | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | Yes | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 220 | 60.27 |
| Total Bits | 8576 | 5531 | 64.49 |
| Total Bits 0->1 | 4288 | 2793 | 65.14 |
| Total Bits 1->0 | 4288 | 2738 | 63.85 |
| Ports | 28 | 18 | 64.29 |
| Port Bits | 6838 | 4597 | 67.23 |
| Port Bits 0->1 | 3419 | 2297 | 67.18 |
| Port Bits 1->0 | 3419 | 2300 | 67.27 |
| Signals | 337 | 202 | 59.94 |
| Signal Bits | 1738 | 934 | 53.74 |
| Signal Bits 0->1 | 869 | 496 | 57.08 |
| Signal Bits 1->0 | 869 | 438 | 50.40 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[4:9] | Yes | Yes | Yes | INPUT |
| clb_I2[3] | No | Yes | No | INPUT |
| clb_I2[0:2] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | Yes | Yes | Yes | INPUT |
| clb_I3[8] | No | Yes | No | INPUT |
| clb_I3[7] | Yes | Yes | Yes | INPUT |
| clb_I3[6] | No | Yes | No | INPUT |
| clb_I3[5] | Yes | Yes | Yes | INPUT |
| clb_I3[4] | No | Yes | No | INPUT |
| clb_I3[0:3] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | No | No | No | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | No | No |
| mux_tree_size20_11_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:2] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | No |
| mux_tree_size20_14_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1] | No | Yes | No |
| mux_tree_size20_14_sram[0] | No | No | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[3] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[3] | No | No | Yes |
| mux_tree_size20_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[2] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | No | No | Yes |
| mux_tree_size20_19_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | No | No | Yes |
| mux_tree_size20_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | Yes | No |
| mux_tree_size20_23_sram[3] | No | No | No |
| mux_tree_size20_23_sram[1:2] | No | Yes | No |
| mux_tree_size20_23_sram[0] | No | No | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[3] | No | No | Yes |
| mux_tree_size20_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[2] | No | No | No |
| mux_tree_size20_29_sram[0:1] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:2] | No | Yes | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:1] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | No | Yes | No |
| mux_tree_size20_5_sram[0:2] | No | No | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0:1] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | No | No |
| mux_tree_size20_8_sram[1] | No | No | Yes |
| mux_tree_size20_8_sram[0] | No | No | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:2] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | Yes | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | No | No | Yes |
| mux_tree_size30_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:2] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | No | No | Yes |
| mux_tree_size30_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[2] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | No | No | Yes |
| mux_tree_size30_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[1:2] | No | No | Yes |
| mux_tree_size30_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[3] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[1:4] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[0:1] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[1] | No | No | Yes |
| mux_tree_size4_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | Yes | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | No | Yes | No |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | No | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 238 | 65.21 |
| Total Bits | 8576 | 5592 | 65.21 |
| Total Bits 0->1 | 4288 | 2825 | 65.88 |
| Total Bits 1->0 | 4288 | 2767 | 64.53 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4604 | 67.33 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 217 | 64.39 |
| Signal Bits | 1738 | 988 | 56.85 |
| Signal Bits 0->1 | 869 | 523 | 60.18 |
| Signal Bits 1->0 | 869 | 465 | 53.51 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[9] | No | Yes | No | INPUT |
| clb_I2[0:8] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[1:2] | No | No | Yes |
| mux_tree_size20_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:3] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[2] | No | No | Yes |
| mux_tree_size20_12_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | Yes | No |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | No | No | Yes |
| mux_tree_size20_13_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1] | No | Yes | No |
| mux_tree_size20_14_sram[0] | No | No | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[2] | No | Yes | No |
| mux_tree_size20_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0] | No | Yes | No |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[3] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[1:2] | No | No | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | No | Yes |
| mux_tree_size20_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:2] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[3] | No | No | Yes |
| mux_tree_size20_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1] | No | No | Yes |
| mux_tree_size20_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | No | Yes |
| mux_tree_size20_8_sram[0] | No | No | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2:3] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | No | No | Yes |
| mux_tree_size30_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | No | No | Yes |
| mux_tree_size30_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | No | No | Yes |
| mux_tree_size30_19_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[2] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[3] | No | No | Yes |
| mux_tree_size30_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | No | No | Yes |
| mux_tree_size30_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:2] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | No | No | Yes |
| mux_tree_size30_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:1] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[2] | No | No | Yes |
| mux_tree_size30_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | No | No | Yes |
| mux_tree_size30_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[2:3] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0:1] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[1] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | Yes | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | No | Yes | No |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 230 | 63.01 |
| Total Bits | 8576 | 5560 | 64.83 |
| Total Bits 0->1 | 4288 | 2810 | 65.53 |
| Total Bits 1->0 | 4288 | 2750 | 64.13 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4604 | 67.33 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 209 | 62.02 |
| Signal Bits | 1738 | 956 | 55.01 |
| Signal Bits 0->1 | 869 | 508 | 58.46 |
| Signal Bits 1->0 | 869 | 448 | 51.55 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[1:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0] | No | Yes | No | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[3] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[2] | No | No | No |
| mux_tree_size20_11_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[2] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:1] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[0:1] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[1:4] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:3] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[2] | No | No | Yes |
| mux_tree_size20_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[0:2] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[2:4] | No | No | Yes |
| mux_tree_size20_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[3] | No | Yes | No |
| mux_tree_size20_23_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[1] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | No | No |
| mux_tree_size20_26_sram[3] | No | No | Yes |
| mux_tree_size20_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | No | No | Yes |
| mux_tree_size20_27_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | Yes | No |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | Yes | No |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[3] | No | No | Yes |
| mux_tree_size20_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | Yes | No |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | No | No | No |
| mux_tree_size20_5_sram[0:1] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | No | Yes | No |
| mux_tree_size20_8_sram[0] | No | No | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | No | No | Yes |
| mux_tree_size30_10_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[1] | No | No | Yes |
| mux_tree_size30_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[3:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | No | No | Yes |
| mux_tree_size30_15_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[1] | No | No | Yes |
| mux_tree_size30_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | No | No | Yes |
| mux_tree_size30_16_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[2] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:2] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[2:3] | No | No | Yes |
| mux_tree_size30_20_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | No | No | Yes |
| mux_tree_size30_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | No | No | Yes |
| mux_tree_size30_4_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0:1] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[1] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[1] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[0] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | No | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | Yes | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 237 | 64.93 |
| Total Bits | 8576 | 5576 | 65.02 |
| Total Bits 0->1 | 4288 | 2824 | 65.86 |
| Total Bits 1->0 | 4288 | 2752 | 64.18 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 215 | 63.80 |
| Signal Bits | 1738 | 971 | 55.87 |
| Signal Bits 0->1 | 869 | 521 | 59.95 |
| Signal Bits 1->0 | 869 | 450 | 51.78 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:4] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[3] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | Yes | No |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0:1] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | No | No | Yes |
| mux_tree_size20_15_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[3] | No | No | Yes |
| mux_tree_size20_16_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[2] | No | No | Yes |
| mux_tree_size20_17_sram[1] | No | Yes | No |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1:3] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | No | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | No | Yes |
| mux_tree_size20_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | No |
| mux_tree_size20_26_sram[2] | No | Yes | No |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0:1] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[2] | No | Yes | No |
| mux_tree_size20_2_sram[1] | No | No | No |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[2:3] | No | No | Yes |
| mux_tree_size20_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[2:3] | No | No | Yes |
| mux_tree_size20_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[0] | No | No | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:3] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[1:3] | No | No | Yes |
| mux_tree_size30_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[3] | No | No | Yes |
| mux_tree_size30_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[3] | No | No | Yes |
| mux_tree_size30_17_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[2:4] | No | No | Yes |
| mux_tree_size30_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | No | No | Yes |
| mux_tree_size30_21_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2:3] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | No | No | Yes |
| mux_tree_size30_23_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0:2] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:2] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[1:2] | No | No | Yes |
| mux_tree_size30_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[1] | No | No | Yes |
| mux_tree_size30_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[1] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | No | No | Yes |
| mux_tree_size4_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | No | No | Yes |
| mux_tree_size4_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | No | No | Yes |
| mux_tree_size4_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | Yes | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | No | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 234 | 64.11 |
| Total Bits | 8576 | 5569 | 64.94 |
| Total Bits 0->1 | 4288 | 2826 | 65.90 |
| Total Bits 1->0 | 4288 | 2743 | 63.97 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 212 | 62.91 |
| Signal Bits | 1738 | 964 | 55.47 |
| Signal Bits 0->1 | 869 | 523 | 60.18 |
| Signal Bits 1->0 | 869 | 441 | 50.75 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[1:2] | No | No | Yes |
| mux_tree_size20_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[0:2] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | No | Yes | No |
| mux_tree_size20_14_sram[1:2] | No | No | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2:3] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0:1] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | No | No | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[3] | No | Yes | No |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1:2] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0:2] | No | No | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[2] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | No | No | Yes |
| mux_tree_size20_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1:2] | No | No | Yes |
| mux_tree_size20_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0:2] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:2] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[3] | No | No | Yes |
| mux_tree_size30_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[3] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[3] | No | No | Yes |
| mux_tree_size30_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0:1] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[3] | No | No | Yes |
| mux_tree_size30_21_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[2:4] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:3] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0:3] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[3] | No | No | Yes |
| mux_tree_size30_28_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0:3] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0:1] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | No | No | Yes |
| mux_tree_size4_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[0] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[1] | No | No | Yes |
| mux_tree_size4_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0:1] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | No | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 241 | 66.03 |
| Total Bits | 8576 | 5589 | 65.17 |
| Total Bits 0->1 | 4288 | 2834 | 66.09 |
| Total Bits 1->0 | 4288 | 2755 | 64.25 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 219 | 64.99 |
| Signal Bits | 1738 | 984 | 56.62 |
| Signal Bits 0->1 | 869 | 531 | 61.10 |
| Signal Bits 1->0 | 869 | 453 | 52.13 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[2] | No | No | Yes |
| mux_tree_size20_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:1] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | Yes | No |
| mux_tree_size20_14_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[3] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1] | No | No | Yes |
| mux_tree_size20_17_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[2:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0:1] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | No | Yes |
| mux_tree_size20_20_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | No | No | Yes |
| mux_tree_size20_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | No | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[3] | No | No | Yes |
| mux_tree_size20_24_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | No | No | Yes |
| mux_tree_size20_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | No | Yes |
| mux_tree_size20_26_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0:2] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0:1] | No | No | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1] | No | No | No |
| mux_tree_size20_5_sram[0] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0:1] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[2:3] | No | No | Yes |
| mux_tree_size30_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[3] | No | No | Yes |
| mux_tree_size30_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[2] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:1] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[2] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | No | No | Yes |
| mux_tree_size30_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | No | No | Yes |
| mux_tree_size30_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:2] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:2] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[2:3] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2] | No | No | Yes |
| mux_tree_size30_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[2] | No | No | Yes |
| mux_tree_size30_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:1] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0:1] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0:1] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[1] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 219 | 60.00 |
| Total Bits | 8576 | 5561 | 64.84 |
| Total Bits 0->1 | 4288 | 2819 | 65.74 |
| Total Bits 1->0 | 4288 | 2742 | 63.95 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 198 | 58.75 |
| Signal Bits | 1738 | 958 | 55.12 |
| Signal Bits 0->1 | 869 | 517 | 59.49 |
| Signal Bits 1->0 | 869 | 441 | 50.75 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2:3] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0:2] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[2:3] | No | No | Yes |
| mux_tree_size20_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1:2] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:1] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0:1] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0:2] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[3] | No | No | Yes |
| mux_tree_size20_29_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[2:4] | No | No | Yes |
| mux_tree_size20_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[2:3] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[3] | No | No | Yes |
| mux_tree_size20_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0:2] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[1] | No | No | Yes |
| mux_tree_size30_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[3] | No | No | Yes |
| mux_tree_size30_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[2] | No | No | Yes |
| mux_tree_size30_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:3] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[1] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[0:1] | No | No | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[1] | No | No | Yes |
| mux_tree_size30_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0:1] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[3] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[1:3] | No | No | Yes |
| mux_tree_size30_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1:2] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[3] | No | No | Yes |
| mux_tree_size30_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[1] | No | No | Yes |
| mux_tree_size30_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:1] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0:1] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[1] | No | No | Yes |
| mux_tree_size30_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[0] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | No | No | Yes |
| mux_tree_size30_7_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[3] | No | No | Yes |
| mux_tree_size30_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[0] | No | No | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | No | No | Yes |
| mux_tree_size4_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[2] | No | No | Yes |
| mux_tree_size4_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0:1] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | Yes | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | No | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | Yes | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 228 | 62.47 |
| Total Bits | 8576 | 5547 | 64.68 |
| Total Bits 0->1 | 4288 | 2817 | 65.69 |
| Total Bits 1->0 | 4288 | 2730 | 63.67 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 207 | 61.42 |
| Signal Bits | 1738 | 944 | 54.32 |
| Signal Bits 0->1 | 869 | 515 | 59.26 |
| Signal Bits 1->0 | 869 | 429 | 49.37 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | No | Yes |
| mux_tree_size20_11_sram[3] | No | Yes | No |
| mux_tree_size20_11_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | No | No | Yes |
| mux_tree_size20_14_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1] | No | No | Yes |
| mux_tree_size20_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0:2] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | No | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[2] | No | No | Yes |
| mux_tree_size20_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | No | No | Yes |
| mux_tree_size20_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0:1] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | No | No | Yes |
| mux_tree_size20_21_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0:1] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[1] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[3] | No | Yes | No |
| mux_tree_size20_26_sram[1:2] | No | No | No |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0:2] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | Yes |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0:2] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:2] | No | Yes | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | No | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | No | No | Yes |
| mux_tree_size20_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | No | No | Yes |
| mux_tree_size20_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | Yes | No |
| mux_tree_size20_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0:2] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:2] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[3:4] | No | No | Yes |
| mux_tree_size30_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[2:3] | No | No | Yes |
| mux_tree_size30_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | No | No | Yes |
| mux_tree_size30_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2:3] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | No | No | Yes |
| mux_tree_size30_18_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[0:2] | No | No | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[1:2] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | No | No | Yes |
| mux_tree_size30_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:1] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[2] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | No | No | Yes |
| mux_tree_size30_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | No | No | Yes |
| mux_tree_size30_26_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | No | No | Yes |
| mux_tree_size30_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | No | No | Yes |
| mux_tree_size4_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram[0:1] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | Yes | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | No | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 230 | 63.01 |
| Total Bits | 8576 | 5567 | 64.91 |
| Total Bits 0->1 | 4288 | 2821 | 65.79 |
| Total Bits 1->0 | 4288 | 2746 | 64.04 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 209 | 62.02 |
| Signal Bits | 1738 | 964 | 55.47 |
| Signal Bits 0->1 | 869 | 519 | 59.72 |
| Signal Bits 1->0 | 869 | 445 | 51.21 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[2:4] | No | No | Yes |
| mux_tree_size20_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[2] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[1:3] | No | No | Yes |
| mux_tree_size20_17_sram[0] | No | No | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0:1] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1:3] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[2] | No | No | Yes |
| mux_tree_size20_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | No | No | Yes |
| mux_tree_size20_26_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[3] | No | No | Yes |
| mux_tree_size20_28_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[0] | No | No | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[3] | No | No | Yes |
| mux_tree_size20_29_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | No | Yes |
| mux_tree_size20_2_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1:2] | No | No | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[2] | No | No | Yes |
| mux_tree_size20_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[2] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[1] | No | No | Yes |
| mux_tree_size30_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | No | No | Yes |
| mux_tree_size30_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:1] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[1:3] | No | No | Yes |
| mux_tree_size30_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[1] | No | No | Yes |
| mux_tree_size30_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[2] | No | No | Yes |
| mux_tree_size30_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[1:2] | No | No | Yes |
| mux_tree_size30_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[2] | No | No | Yes |
| mux_tree_size30_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1:3] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[2:3] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[3] | No | No | Yes |
| mux_tree_size30_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[1:4] | No | No | Yes |
| mux_tree_size30_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[3] | No | No | Yes |
| mux_tree_size30_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[2:3] | No | No | Yes |
| mux_tree_size30_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[2] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0:1] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 220 | 60.27 |
| Total Bits | 8576 | 5558 | 64.81 |
| Total Bits 0->1 | 4288 | 2820 | 65.76 |
| Total Bits 1->0 | 4288 | 2738 | 63.85 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 199 | 59.05 |
| Signal Bits | 1738 | 955 | 54.95 |
| Signal Bits 0->1 | 869 | 518 | 59.61 |
| Signal Bits 1->0 | 869 | 437 | 50.29 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | No | No | Yes |
| mux_tree_size20_11_sram[2] | No | No | No |
| mux_tree_size20_11_sram[0:1] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[3] | No | No | Yes |
| mux_tree_size20_12_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1:2] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[3] | No | No | Yes |
| mux_tree_size20_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[1:3] | No | No | Yes |
| mux_tree_size20_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[3:4] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | No | No | Yes |
| mux_tree_size20_24_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[2:3] | No | No | Yes |
| mux_tree_size20_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[2] | No | No | Yes |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[2:3] | No | No | Yes |
| mux_tree_size20_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:2] | No | Yes | No |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | No | No | Yes |
| mux_tree_size20_5_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | No | No | Yes |
| mux_tree_size20_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[0] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1:2] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram[0] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[2] | No | No | Yes |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[0:1] | No | No | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[1:2] | No | No | Yes |
| mux_tree_size30_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[1] | No | No | Yes |
| mux_tree_size30_16_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[2:4] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[3] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[3] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[1] | No | No | Yes |
| mux_tree_size30_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[1:2] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0:2] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[3] | No | No | Yes |
| mux_tree_size30_25_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[3] | No | No | Yes |
| mux_tree_size30_26_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[2] | No | No | Yes |
| mux_tree_size30_27_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | No | No | Yes |
| mux_tree_size30_28_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:3] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[2] | No | No | Yes |
| mux_tree_size30_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | No | No | Yes |
| mux_tree_size30_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[3] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[2:3] | No | No | Yes |
| mux_tree_size30_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[2] | No | No | Yes |
| mux_tree_size4_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram[0] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[2] | No | No | Yes |
| mux_tree_size4_5_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | No | No | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | Yes | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | Yes | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 243 | 66.58 |
| Total Bits | 8576 | 5584 | 65.11 |
| Total Bits 0->1 | 4288 | 2818 | 65.72 |
| Total Bits 1->0 | 4288 | 2766 | 64.51 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 222 | 65.88 |
| Signal Bits | 1738 | 981 | 56.44 |
| Signal Bits 0->1 | 869 | 516 | 59.38 |
| Signal Bits 1->0 | 869 | 465 | 53.51 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | No | No | Yes |
| mux_tree_size20_11_sram[1] | No | No | No |
| mux_tree_size20_11_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[0] | No | No | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[1:2] | No | No | Yes |
| mux_tree_size20_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[2:3] | No | No | Yes |
| mux_tree_size20_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | No | No | Yes |
| mux_tree_size20_20_sram[3] | No | No | No |
| mux_tree_size20_20_sram[1:2] | No | No | Yes |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0:3] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | Yes | No |
| mux_tree_size20_23_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[4] | No | No | Yes |
| mux_tree_size20_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[2:3] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | No | Yes | No |
| mux_tree_size20_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1] | No | No | Yes |
| mux_tree_size20_2_sram[0] | No | No | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | No | Yes |
| mux_tree_size20_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | No | No | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[2:3] | No | No | Yes |
| mux_tree_size30_11_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | No | Yes |
| mux_tree_size30_13_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0:1] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[1:3] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[0:2] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[0] | No | No | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[3] | No | No | Yes |
| mux_tree_size30_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | No | No | Yes |
| mux_tree_size30_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[1] | No | No | Yes |
| mux_tree_size4_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | Yes | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 223 | 61.10 |
| Total Bits | 8576 | 5542 | 64.62 |
| Total Bits 0->1 | 4288 | 2802 | 65.35 |
| Total Bits 1->0 | 4288 | 2740 | 63.90 |
| Ports | 28 | 21 | 75.00 |
| Port Bits | 6838 | 4603 | 67.32 |
| Port Bits 0->1 | 3419 | 2302 | 67.33 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 202 | 59.94 |
| Signal Bits | 1738 | 939 | 54.03 |
| Signal Bits 0->1 | 869 | 500 | 57.54 |
| Signal Bits 1->0 | 869 | 439 | 50.52 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0:1] | No | No | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1:3] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[1] | No | No | Yes |
| mux_tree_size20_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[2:3] | No | No | Yes |
| mux_tree_size20_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[3] | No | No | Yes |
| mux_tree_size20_17_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | No | No | Yes |
| mux_tree_size20_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[3:4] | No | No | Yes |
| mux_tree_size20_19_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1:2] | No | Yes | No |
| mux_tree_size20_20_sram[0] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | Yes | No |
| mux_tree_size20_23_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | Yes | No |
| mux_tree_size20_23_sram[1] | No | No | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram[0] | No | No | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[2] | No | No | Yes |
| mux_tree_size20_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | No | Yes |
| mux_tree_size20_26_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[2] | No | Yes | No |
| mux_tree_size20_26_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[3] | No | No | Yes |
| mux_tree_size20_28_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[3] | No | Yes | No |
| mux_tree_size20_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0] | No | No | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:2] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[3:4] | No | No | Yes |
| mux_tree_size20_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[3] | No | No | Yes |
| mux_tree_size20_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | No | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1:2] | No | No | Yes |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[2] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | Yes | No |
| mux_tree_size20_8_sram[3] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | Yes | No |
| mux_tree_size20_8_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[3] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:3] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[3:4] | No | No | Yes |
| mux_tree_size30_16_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[1:4] | No | No | Yes |
| mux_tree_size30_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[0:3] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[1:4] | No | No | Yes |
| mux_tree_size30_23_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[3] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[0:1] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0:1] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[3:4] | No | No | Yes |
| mux_tree_size30_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | No | No | Yes |
| mux_tree_size30_9_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[1] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[0:2] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[2] | No | No | Yes |
| mux_tree_size4_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | Yes | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | Yes | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | No | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | No | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | Yes | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 213 | 58.36 |
| Total Bits | 8576 | 5525 | 64.42 |
| Total Bits 0->1 | 4288 | 2779 | 64.81 |
| Total Bits 1->0 | 4288 | 2746 | 64.04 |
| Ports | 28 | 19 | 67.86 |
| Port Bits | 6838 | 4596 | 67.21 |
| Port Bits 0->1 | 3419 | 2298 | 67.21 |
| Port Bits 1->0 | 3419 | 2298 | 67.21 |
| Signals | 337 | 194 | 57.57 |
| Signal Bits | 1738 | 929 | 53.45 |
| Signal Bits 0->1 | 869 | 481 | 55.35 |
| Signal Bits 1->0 | 869 | 448 | 51.55 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | No | Yes | No | INPUT |
| clb_I3[8] | No | No | No | INPUT |
| clb_I3[5:7] | Yes | Yes | Yes | INPUT |
| clb_I3[4] | No | No | No | INPUT |
| clb_I3[0:3] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | No | No | No | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[4] | No | No | Yes |
| mux_tree_size20_10_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | Yes | No |
| mux_tree_size20_11_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[1] | No | No | Yes |
| mux_tree_size20_11_sram[0] | No | No | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[2] | No | No | Yes |
| mux_tree_size20_12_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[3] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram[0:1] | No | No | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | No | No | Yes |
| mux_tree_size20_17_sram[3] | No | Yes | No |
| mux_tree_size20_17_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[1:3] | No | Yes | No |
| mux_tree_size20_23_sram[0] | No | No | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | Yes | No |
| mux_tree_size20_26_sram[3] | No | No | No |
| mux_tree_size20_26_sram[0:2] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[1] | No | No | No |
| mux_tree_size20_28_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:2] | No | No | Yes |
| mux_tree_size20_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[0:1] | No | No | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[3] | No | No | Yes |
| mux_tree_size20_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | No | No | Yes |
| mux_tree_size20_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[2] | No | No | Yes |
| mux_tree_size20_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[0:4] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | Yes | No |
| mux_tree_size2_0_sram[0] | No | No | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram[1] | No | No | Yes |
| mux_tree_size30_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:1] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:1] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | No | No | Yes |
| mux_tree_size30_14_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:2] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[3] | No | No | Yes |
| mux_tree_size30_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[1:2] | No | No | Yes |
| mux_tree_size30_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[4] | No | No | Yes |
| mux_tree_size30_21_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[3:4] | No | No | Yes |
| mux_tree_size30_22_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[2] | No | No | Yes |
| mux_tree_size30_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2:3] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | No | No | Yes |
| mux_tree_size30_26_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[1] | No | No | Yes |
| mux_tree_size30_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[3] | No | No | Yes |
| mux_tree_size30_27_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[2:3] | No | No | Yes |
| mux_tree_size30_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[1:2] | No | No | Yes |
| mux_tree_size30_29_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | No | No | Yes |
| mux_tree_size30_2_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | No | No | Yes |
| mux_tree_size30_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[3:4] | No | No | Yes |
| mux_tree_size30_4_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[0] | No | No | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | No | No | Yes |
| mux_tree_size30_8_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[0:1] | No | No | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[1:2] | No | No | Yes |
| mux_tree_size4_2_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0:1] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[2] | No | No | Yes |
| mux_tree_size4_6_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram[0] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | No | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | No | No | No |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | No | Yes | No |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | No | No |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | Yes | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | No | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | No | No | No |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 206 | 56.44 |
| Total Bits | 8576 | 5485 | 63.96 |
| Total Bits 0->1 | 4288 | 2766 | 64.51 |
| Total Bits 1->0 | 4288 | 2719 | 63.41 |
| Ports | 28 | 19 | 67.86 |
| Port Bits | 6838 | 4592 | 67.15 |
| Port Bits 0->1 | 3419 | 2294 | 67.10 |
| Port Bits 1->0 | 3419 | 2298 | 67.21 |
| Signals | 337 | 187 | 55.49 |
| Signal Bits | 1738 | 893 | 51.38 |
| Signal Bits 0->1 | 869 | 472 | 54.32 |
| Signal Bits 1->0 | 869 | 421 | 48.45 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[8:9] | No | Yes | No | INPUT |
| clb_I2[4:7] | Yes | Yes | Yes | INPUT |
| clb_I2[3] | No | Yes | No | INPUT |
| clb_I2[0:2] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | No | No | No | INPUT |
| clb_I3[8] | Yes | Yes | Yes | INPUT |
| clb_I3[7] | No | No | No | INPUT |
| clb_I3[6] | Yes | Yes | Yes | INPUT |
| clb_I3[5] | No | No | No | INPUT |
| clb_I3[4] | No | Yes | No | INPUT |
| clb_I3[3] | Yes | Yes | Yes | INPUT |
| clb_I3[2] | No | Yes | No | INPUT |
| clb_I3[0:1] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | No | No | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | Yes | No |
| mux_tree_size20_11_sram[3] | No | No | Yes |
| mux_tree_size20_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[1:2] | No | No | Yes |
| mux_tree_size20_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | No | Yes | No |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[0] | No | Yes | No |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[1:4] | No | No | Yes |
| mux_tree_size20_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0:1] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[0:2] | No | No | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1:3] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[0:4] | No | Yes | No |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | No | No | Yes |
| mux_tree_size20_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[4] | No | Yes | No |
| mux_tree_size20_23_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0:1] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[1:4] | No | No | Yes |
| mux_tree_size20_25_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[4] | No | Yes | No |
| mux_tree_size20_26_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | No | Yes |
| mux_tree_size20_26_sram[0] | No | No | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_28_sram[2] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[2:3] | No | Yes | No |
| mux_tree_size20_29_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0] | No | Yes | No |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[3:4] | No | Yes | No |
| mux_tree_size20_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[0:1] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[3] | No | No | Yes |
| mux_tree_size20_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[3] | No | Yes | No |
| mux_tree_size20_4_sram[2] | No | No | Yes |
| mux_tree_size20_4_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[0] | No | Yes | No |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[0:4] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1] | No | Yes | No |
| mux_tree_size20_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | No | No | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[4] | No | Yes | No |
| mux_tree_size20_8_sram[3] | No | No | Yes |
| mux_tree_size20_8_sram[2] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[0:1] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[4] | No | No | Yes |
| mux_tree_size20_9_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | Yes | No |
| mux_tree_size2_0_sram[0] | No | No | No |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[2] | No | Yes | No |
| mux_tree_size30_10_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | No | No | Yes |
| mux_tree_size30_11_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0:1] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:1] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[4] | No | Yes | No |
| mux_tree_size30_13_sram[3] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[2] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | No | No | Yes |
| mux_tree_size30_14_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[4] | No | No | Yes |
| mux_tree_size30_17_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:2] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[1] | No | No | Yes |
| mux_tree_size30_19_sram[0] | No | Yes | No |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram[3] | No | No | Yes |
| mux_tree_size30_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[1:2] | No | No | Yes |
| mux_tree_size30_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram[2] | No | No | Yes |
| mux_tree_size30_22_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0:1] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[2] | No | No | Yes |
| mux_tree_size30_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[1] | No | No | Yes |
| mux_tree_size30_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1] | No | No | No |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0:3] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[2] | No | Yes | No |
| mux_tree_size30_3_sram[1] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | Yes | No |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram[2:3] | No | No | Yes |
| mux_tree_size30_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[1:4] | No | No | Yes |
| mux_tree_size30_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[3] | No | No | Yes |
| mux_tree_size30_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[1:4] | No | No | Yes |
| mux_tree_size30_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[2] | No | No | Yes |
| mux_tree_size4_1_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram[0:1] | No | No | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | No | No | Yes |
| mux_tree_size4_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | No | No | Yes |
| set | Yes | Yes | Yes |
| rst | No | No | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | No | No | No |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | No | No | No |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | No | No | No |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | No | No | No |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | No | Yes | No |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | No | No | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | No | No | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | No | No | No |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | No | No | No |
| direct_interc_70_out | No | No | No |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | No | No | No |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | No | No | No |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 223 | 61.10 |
| Total Bits | 8576 | 5561 | 64.84 |
| Total Bits 0->1 | 4288 | 2814 | 65.62 |
| Total Bits 1->0 | 4288 | 2747 | 64.06 |
| Ports | 28 | 20 | 71.43 |
| Port Bits | 6838 | 4602 | 67.30 |
| Port Bits 0->1 | 3419 | 2301 | 67.30 |
| Port Bits 1->0 | 3419 | 2301 | 67.30 |
| Signals | 337 | 203 | 60.24 |
| Signal Bits | 1738 | 959 | 55.18 |
| Signal Bits 0->1 | 869 | 513 | 59.03 |
| Signal Bits 1->0 | 869 | 446 | 51.32 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[9] | No | Yes | No | INPUT |
| clb_I3[0:8] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | No | No | No | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[2] | No | No | Yes |
| mux_tree_size20_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[4] | No | No | Yes |
| mux_tree_size20_11_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[2] | No | No | Yes |
| mux_tree_size20_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[0:1] | No | No | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[4] | No | No | Yes |
| mux_tree_size20_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | No | Yes | No |
| mux_tree_size20_17_sram[2] | No | No | No |
| mux_tree_size20_17_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[3] | No | No | Yes |
| mux_tree_size20_19_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_19_sram[0] | No | No | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[1:2] | No | Yes | No |
| mux_tree_size20_20_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[0] | No | Yes | No |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[4] | No | No | Yes |
| mux_tree_size20_24_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | No | No | Yes |
| mux_tree_size20_25_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[0] | No | No | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[1] | No | Yes | No |
| mux_tree_size20_26_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[4] | No | No | Yes |
| mux_tree_size20_27_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[1] | No | No | Yes |
| mux_tree_size20_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[2:4] | No | No | Yes |
| mux_tree_size20_28_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram[0:2] | No | No | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1:3] | No | No | Yes |
| mux_tree_size20_2_sram[0] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[1] | No | No | Yes |
| mux_tree_size20_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[1] | No | Yes | No |
| mux_tree_size20_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[1] | No | No | Yes |
| mux_tree_size20_6_sram[0] | No | No | No |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[4] | No | No | Yes |
| mux_tree_size20_7_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[1] | No | Yes | No |
| mux_tree_size20_8_sram[0] | No | No | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[1:2] | No | No | Yes |
| mux_tree_size20_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0:2] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[3] | No | No | Yes |
| mux_tree_size30_11_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_11_sram[0] | No | No | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[1] | No | No | Yes |
| mux_tree_size30_12_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram[1] | No | No | Yes |
| mux_tree_size30_13_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[1] | No | No | Yes |
| mux_tree_size30_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[0:1] | No | No | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | No | No | Yes |
| mux_tree_size30_16_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:1] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[1] | No | No | Yes |
| mux_tree_size30_19_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram[1:2] | No | No | Yes |
| mux_tree_size30_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[1:3] | No | No | Yes |
| mux_tree_size30_24_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[4] | No | No | Yes |
| mux_tree_size30_25_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram[0:3] | No | No | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[1:2] | No | No | Yes |
| mux_tree_size30_27_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram[0] | No | No | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[3] | No | No | Yes |
| mux_tree_size30_29_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[4] | No | No | Yes |
| mux_tree_size30_2_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_2_sram[0] | No | No | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[3] | No | No | Yes |
| mux_tree_size30_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[4] | No | No | Yes |
| mux_tree_size30_6_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram[2:3] | No | No | Yes |
| mux_tree_size30_7_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram[0] | No | No | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | No | No | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[2] | No | No | Yes |
| mux_tree_size4_3_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | No | No | Yes |
| mux_tree_size4_4_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram[0] | No | No | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[2] | No | No | Yes |
| mux_tree_size4_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | Yes | Yes | Yes |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | No | No | No |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | No | No | No |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | No | No | No |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | Yes | Yes | Yes |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | No | No | No |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | No | No | No |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | No | No | No |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | No | No | No |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | No | No | No |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | No | No | No |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | No | No | No |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | No | No | No |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 232 | 63.56 |
| Total Bits | 8576 | 5563 | 64.87 |
| Total Bits 0->1 | 4288 | 2827 | 65.93 |
| Total Bits 1->0 | 4288 | 2736 | 63.81 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 210 | 62.31 |
| Signal Bits | 1738 | 958 | 55.12 |
| Signal Bits 0->1 | 869 | 524 | 60.30 |
| Signal Bits 1->0 | 869 | 434 | 49.94 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_10_sram[1] | No | No | Yes |
| mux_tree_size20_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[1:4] | No | No | Yes |
| mux_tree_size20_11_sram[0] | No | Yes | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_12_sram[0] | No | No | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_13_sram[2:3] | No | No | Yes |
| mux_tree_size20_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[1] | No | No | Yes |
| mux_tree_size20_15_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[2:4] | No | No | Yes |
| mux_tree_size20_16_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[3:4] | No | Yes | No |
| mux_tree_size20_17_sram[2] | No | No | No |
| mux_tree_size20_17_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[4] | No | No | Yes |
| mux_tree_size20_18_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[2:4] | No | No | Yes |
| mux_tree_size20_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[1] | No | No | Yes |
| mux_tree_size20_1_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[0:2] | No | No | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[0] | No | No | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_22_sram[0] | No | No | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[3:4] | No | No | Yes |
| mux_tree_size20_24_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[3:4] | No | No | Yes |
| mux_tree_size20_28_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_2_sram[1] | No | Yes | No |
| mux_tree_size20_2_sram[0] | No | No | Yes |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram[1] | No | No | Yes |
| mux_tree_size20_3_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram[1] | No | No | Yes |
| mux_tree_size20_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[3] | No | No | No |
| mux_tree_size20_5_sram[2] | No | No | Yes |
| mux_tree_size20_5_sram[1] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0] | No | Yes | No |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[3] | No | No | Yes |
| mux_tree_size20_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_6_sram[0] | No | Yes | No |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram[1:2] | No | No | Yes |
| mux_tree_size20_7_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | No | Yes |
| mux_tree_size20_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram[0] | No | No | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[1] | No | No | Yes |
| mux_tree_size2_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[1] | No | No | Yes |
| mux_tree_size30_10_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram[0:1] | No | No | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[2:4] | No | No | Yes |
| mux_tree_size30_13_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[0:3] | No | No | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_15_sram[3] | No | No | Yes |
| mux_tree_size30_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[2:4] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | No | No | Yes |
| mux_tree_size30_18_sram[2:3] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[0:1] | No | No | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram[2:3] | No | No | Yes |
| mux_tree_size30_19_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[3:4] | No | No | Yes |
| mux_tree_size30_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[4] | No | No | Yes |
| mux_tree_size30_20_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[2:4] | No | No | Yes |
| mux_tree_size30_21_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[0:4] | No | No | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_23_sram[0] | No | No | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | No | No | Yes |
| mux_tree_size30_24_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram[0] | No | No | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_27_sram[0] | No | No | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[0:2] | No | No | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[2:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[3:4] | No | No | Yes |
| mux_tree_size30_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[1:3] | No | No | Yes |
| mux_tree_size30_5_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_6_sram[1] | No | No | Yes |
| mux_tree_size30_6_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[1:4] | No | No | Yes |
| mux_tree_size30_8_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[3] | No | No | Yes |
| mux_tree_size30_9_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram[0] | No | No | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[1] | No | No | Yes |
| mux_tree_size4_4_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram[0] | No | No | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[1:2] | No | No | Yes |
| mux_tree_size4_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | Yes | Yes | Yes |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | No | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | No | Yes | No |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 365 | 233 | 63.84 |
| Total Bits | 8576 | 5568 | 64.93 |
| Total Bits 0->1 | 4288 | 2821 | 65.79 |
| Total Bits 1->0 | 4288 | 2747 | 64.06 |
| Ports | 28 | 22 | 78.57 |
| Port Bits | 6838 | 4605 | 67.34 |
| Port Bits 0->1 | 3419 | 2303 | 67.36 |
| Port Bits 1->0 | 3419 | 2302 | 67.33 |
| Signals | 337 | 211 | 62.61 |
| Signal Bits | 1738 | 963 | 55.41 |
| Signal Bits 0->1 | 869 | 518 | 59.61 |
| Signal Bits 1->0 | 869 | 445 | 51.21 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| prst | Yes | Yes | Yes | INPUT |
| CFG_DONE | Yes | Yes | Yes | INPUT |
| test_en | No | No | No | INPUT |
| scan_mode | No | No | No | INPUT |
| scan_clk | Yes | Yes | Yes | INPUT |
| clb_I0[0:9] | Yes | Yes | Yes | INPUT |
| clb_I1[0:9] | Yes | Yes | Yes | INPUT |
| clb_I2[0:9] | Yes | Yes | Yes | INPUT |
| clb_I3[0:9] | Yes | Yes | Yes | INPUT |
| clb_sc_in | No | No | No | INPUT |
| clb_cin | Yes | Yes | Yes | INPUT |
| clb_cin_trick | No | No | No | INPUT |
| clb_set | Yes | Yes | Yes | INPUT |
| clb_lreset | Yes | Yes | Yes | INPUT |
| clb_sync_set | Yes | Yes | Yes | INPUT |
| clb_sync_reset | Yes | Yes | Yes | INPUT |
| clb_reset | No | No | Yes | INPUT |
| clb_scan_reset | Yes | Yes | Yes | INPUT |
| clb_enable | Yes | Yes | Yes | INPUT |
| clb_reg_in | Yes | Yes | Yes | INPUT |
| clb_clk[0:3] | Yes | Yes | Yes | INPUT |
| bl[0:1111] | Yes | Yes | Yes | INPUT |
| wl[0:1111] | Yes | Yes | Yes | INPUT |
| wlr[0:1111] | No | No | No | INPUT |
| clb_O[0:19] | Yes | Yes | Yes | OUTPUT |
| clb_sc_out | Yes | Yes | Yes | OUTPUT |
| clb_cout | Yes | Yes | Yes | OUTPUT |
| clb_reg_out | Yes | Yes | Yes | OUTPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| logical_tile_clb_mode_default__fle_0_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_out[0:1] | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_out[0:1] | Yes | Yes | Yes |
| mux_tree_size20_0_sram[4] | No | No | Yes |
| mux_tree_size20_0_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_0_sram_inv[0:4] | No | No | No |
| mux_tree_size20_10_sram[3:4] | No | No | Yes |
| mux_tree_size20_10_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_10_sram_inv[0:4] | No | No | No |
| mux_tree_size20_11_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_11_sram[2] | No | Yes | No |
| mux_tree_size20_11_sram[0:1] | No | No | No |
| mux_tree_size20_11_sram_inv[0:4] | No | No | No |
| mux_tree_size20_12_sram[3:4] | No | No | Yes |
| mux_tree_size20_12_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_12_sram_inv[0:4] | No | No | No |
| mux_tree_size20_13_sram[3:4] | No | No | Yes |
| mux_tree_size20_13_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_13_sram_inv[0:4] | No | No | No |
| mux_tree_size20_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_14_sram[2] | No | No | Yes |
| mux_tree_size20_14_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_14_sram_inv[0:4] | No | No | No |
| mux_tree_size20_15_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_15_sram[3] | No | No | Yes |
| mux_tree_size20_15_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_15_sram_inv[0:4] | No | No | No |
| mux_tree_size20_16_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_16_sram_inv[0:4] | No | No | No |
| mux_tree_size20_17_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[3] | No | Yes | No |
| mux_tree_size20_17_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size20_17_sram[0] | No | Yes | No |
| mux_tree_size20_17_sram_inv[0:4] | No | No | No |
| mux_tree_size20_18_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_18_sram[1:2] | No | No | Yes |
| mux_tree_size20_18_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_18_sram_inv[0:4] | No | No | No |
| mux_tree_size20_19_sram[1:4] | No | No | Yes |
| mux_tree_size20_19_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_19_sram_inv[0:4] | No | No | No |
| mux_tree_size20_1_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_1_sram[3] | No | No | Yes |
| mux_tree_size20_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_1_sram_inv[0:4] | No | No | No |
| mux_tree_size20_20_sram[4] | Yes | Yes | Yes |
| mux_tree_size20_20_sram[3] | No | No | Yes |
| mux_tree_size20_20_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size20_20_sram_inv[0:4] | No | No | No |
| mux_tree_size20_21_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_21_sram[1:2] | No | No | Yes |
| mux_tree_size20_21_sram[0] | Yes | Yes | Yes |
| mux_tree_size20_21_sram_inv[0:4] | No | No | No |
| mux_tree_size20_22_sram[4] | No | No | Yes |
| mux_tree_size20_22_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_22_sram_inv[0:4] | No | No | No |
| mux_tree_size20_23_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_23_sram[2] | No | Yes | No |
| mux_tree_size20_23_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_23_sram_inv[0:4] | No | No | No |
| mux_tree_size20_24_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_24_sram_inv[0:4] | No | No | No |
| mux_tree_size20_25_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_25_sram[2] | No | No | Yes |
| mux_tree_size20_25_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size20_25_sram_inv[0:4] | No | No | No |
| mux_tree_size20_26_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_26_sram[0] | No | Yes | No |
| mux_tree_size20_26_sram_inv[0:4] | No | No | No |
| mux_tree_size20_27_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size20_27_sram[0] | No | No | Yes |
| mux_tree_size20_27_sram_inv[0:4] | No | No | No |
| mux_tree_size20_28_sram[4] | No | No | Yes |
| mux_tree_size20_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_28_sram_inv[0:4] | No | No | No |
| mux_tree_size20_29_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_29_sram_inv[0:4] | No | No | No |
| mux_tree_size20_2_sram[4] | No | Yes | No |
| mux_tree_size20_2_sram[3] | No | No | No |
| mux_tree_size20_2_sram[0:2] | No | Yes | No |
| mux_tree_size20_2_sram_inv[0:4] | No | No | No |
| mux_tree_size20_3_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_3_sram_inv[0:4] | No | No | No |
| mux_tree_size20_4_sram[4] | No | No | Yes |
| mux_tree_size20_4_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size20_4_sram_inv[0:4] | No | No | No |
| mux_tree_size20_5_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size20_5_sram[0:1] | No | No | Yes |
| mux_tree_size20_5_sram_inv[0:4] | No | No | No |
| mux_tree_size20_6_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_6_sram_inv[0:4] | No | No | No |
| mux_tree_size20_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_7_sram_inv[0:4] | No | No | No |
| mux_tree_size20_8_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size20_8_sram[2] | No | Yes | No |
| mux_tree_size20_8_sram[1] | No | No | No |
| mux_tree_size20_8_sram[0] | No | Yes | No |
| mux_tree_size20_8_sram_inv[0:4] | No | No | No |
| mux_tree_size20_9_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size20_9_sram_inv[0:4] | No | No | No |
| mux_tree_size2_0_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size2_0_sram_inv[0:1] | No | No | No |
| mux_tree_size30_0_sram[3:4] | No | No | Yes |
| mux_tree_size30_0_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_0_sram_inv[0:4] | No | No | No |
| mux_tree_size30_10_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_10_sram[0] | No | No | Yes |
| mux_tree_size30_10_sram_inv[0:4] | No | No | No |
| mux_tree_size30_11_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_11_sram_inv[0:4] | No | No | No |
| mux_tree_size30_12_sram[4] | No | No | Yes |
| mux_tree_size30_12_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_12_sram_inv[0:4] | No | No | No |
| mux_tree_size30_13_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_13_sram_inv[0:4] | No | No | No |
| mux_tree_size30_14_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_14_sram[1:2] | No | No | Yes |
| mux_tree_size30_14_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_14_sram_inv[0:4] | No | No | No |
| mux_tree_size30_15_sram[2:4] | No | No | Yes |
| mux_tree_size30_15_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_15_sram_inv[0:4] | No | No | No |
| mux_tree_size30_16_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[3] | No | No | Yes |
| mux_tree_size30_16_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_16_sram[0] | No | No | Yes |
| mux_tree_size30_16_sram_inv[0:4] | No | No | No |
| mux_tree_size30_17_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_17_sram[2] | No | No | Yes |
| mux_tree_size30_17_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_17_sram_inv[0:4] | No | No | No |
| mux_tree_size30_18_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_18_sram[3] | No | No | Yes |
| mux_tree_size30_18_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_18_sram_inv[0:4] | No | No | No |
| mux_tree_size30_19_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_19_sram_inv[0:4] | No | No | No |
| mux_tree_size30_1_sram[4] | No | No | Yes |
| mux_tree_size30_1_sram[1:3] | Yes | Yes | Yes |
| mux_tree_size30_1_sram[0] | No | No | Yes |
| mux_tree_size30_1_sram_inv[0:4] | No | No | No |
| mux_tree_size30_20_sram[0:4] | No | No | Yes |
| mux_tree_size30_20_sram_inv[0:4] | No | No | No |
| mux_tree_size30_21_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_21_sram_inv[0:4] | No | No | No |
| mux_tree_size30_22_sram[1:4] | No | No | Yes |
| mux_tree_size30_22_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_22_sram_inv[0:4] | No | No | No |
| mux_tree_size30_23_sram[3:4] | No | No | Yes |
| mux_tree_size30_23_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_23_sram_inv[0:4] | No | No | No |
| mux_tree_size30_24_sram[2:4] | Yes | Yes | Yes |
| mux_tree_size30_24_sram[0:1] | No | No | Yes |
| mux_tree_size30_24_sram_inv[0:4] | No | No | No |
| mux_tree_size30_25_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_25_sram_inv[0:4] | No | No | No |
| mux_tree_size30_26_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_26_sram_inv[0:4] | No | No | No |
| mux_tree_size30_27_sram[4] | No | No | Yes |
| mux_tree_size30_27_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_27_sram_inv[0:4] | No | No | No |
| mux_tree_size30_28_sram[4] | No | No | Yes |
| mux_tree_size30_28_sram[0:3] | Yes | Yes | Yes |
| mux_tree_size30_28_sram_inv[0:4] | No | No | No |
| mux_tree_size30_29_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_29_sram[2] | No | No | Yes |
| mux_tree_size30_29_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_29_sram_inv[0:4] | No | No | No |
| mux_tree_size30_2_sram[3:4] | No | No | Yes |
| mux_tree_size30_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size30_2_sram_inv[0:4] | No | No | No |
| mux_tree_size30_3_sram[1:4] | Yes | Yes | Yes |
| mux_tree_size30_3_sram[0] | No | No | Yes |
| mux_tree_size30_3_sram_inv[0:4] | No | No | No |
| mux_tree_size30_4_sram[0:4] | No | No | Yes |
| mux_tree_size30_4_sram_inv[0:4] | No | No | No |
| mux_tree_size30_5_sram[3:4] | No | No | Yes |
| mux_tree_size30_5_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size30_5_sram[0] | No | No | Yes |
| mux_tree_size30_5_sram_inv[0:4] | No | No | No |
| mux_tree_size30_6_sram[0:4] | No | No | Yes |
| mux_tree_size30_6_sram_inv[0:4] | No | No | No |
| mux_tree_size30_7_sram[0:4] | Yes | Yes | Yes |
| mux_tree_size30_7_sram_inv[0:4] | No | No | No |
| mux_tree_size30_8_sram[4] | Yes | Yes | Yes |
| mux_tree_size30_8_sram[2:3] | No | No | Yes |
| mux_tree_size30_8_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size30_8_sram_inv[0:4] | No | No | No |
| mux_tree_size30_9_sram[3:4] | Yes | Yes | Yes |
| mux_tree_size30_9_sram[1:2] | No | No | Yes |
| mux_tree_size30_9_sram[0] | Yes | Yes | Yes |
| mux_tree_size30_9_sram_inv[0:4] | No | No | No |
| mux_tree_size4_0_sram[1:2] | No | No | Yes |
| mux_tree_size4_0_sram[0] | Yes | Yes | Yes |
| mux_tree_size4_0_sram_inv[0:2] | No | No | No |
| mux_tree_size4_1_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_1_sram_inv[0:2] | No | No | No |
| mux_tree_size4_2_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_2_sram_inv[0:2] | No | No | No |
| mux_tree_size4_3_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_3_sram_inv[0:2] | No | No | No |
| mux_tree_size4_4_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_4_sram[0] | No | No | Yes |
| mux_tree_size4_4_sram_inv[0:2] | No | No | No |
| mux_tree_size4_5_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_5_sram_inv[0:2] | No | No | No |
| mux_tree_size4_6_sram[0:2] | Yes | Yes | Yes |
| mux_tree_size4_6_sram_inv[0:2] | No | No | No |
| mux_tree_size4_7_sram[1:2] | Yes | Yes | Yes |
| mux_tree_size4_7_sram[0] | No | No | Yes |
| mux_tree_size4_7_sram_inv[0:2] | No | No | No |
| mux_tree_size4_8_sram[0:2] | No | No | Yes |
| mux_tree_size4_8_sram_inv[0:2] | No | No | No |
| mux_tree_size4_9_sram[2] | No | No | Yes |
| mux_tree_size4_9_sram[0:1] | Yes | Yes | Yes |
| mux_tree_size4_9_sram_inv[0:2] | No | No | No |
| and_rst | Yes | Yes | Yes |
| set | Yes | Yes | Yes |
| rst | Yes | Yes | Yes |
| clb_lreset_b | Yes | Yes | Yes |
| clb_lreset_q | Yes | Yes | Yes |
| mux_tree_size30_0_out | Yes | Yes | Yes |
| mux_tree_size30_1_out | Yes | Yes | Yes |
| mux_tree_size30_2_out | Yes | Yes | Yes |
| mux_tree_size20_0_out | Yes | Yes | Yes |
| mux_tree_size20_1_out | Yes | Yes | Yes |
| mux_tree_size20_2_out | No | No | No |
| mux_tree_size2_0_out | Yes | Yes | Yes |
| direct_interc_23_out | No | No | No |
| direct_interc_26_out | Yes | Yes | Yes |
| direct_interc_27_out | Yes | Yes | Yes |
| direct_interc_28_out | Yes | Yes | Yes |
| direct_interc_29_out | Yes | Yes | Yes |
| mux_tree_size4_0_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_0_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_3_out | Yes | Yes | Yes |
| mux_tree_size30_4_out | Yes | Yes | Yes |
| mux_tree_size30_5_out | Yes | Yes | Yes |
| mux_tree_size20_3_out | Yes | Yes | Yes |
| mux_tree_size20_4_out | Yes | Yes | Yes |
| mux_tree_size20_5_out | Yes | Yes | Yes |
| direct_interc_30_out | Yes | Yes | Yes |
| direct_interc_31_out | Yes | Yes | Yes |
| direct_interc_34_out | Yes | Yes | Yes |
| direct_interc_35_out | Yes | Yes | Yes |
| direct_interc_36_out | Yes | Yes | Yes |
| direct_interc_37_out | Yes | Yes | Yes |
| mux_tree_size4_1_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_1_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_6_out | Yes | Yes | Yes |
| mux_tree_size30_7_out | Yes | Yes | Yes |
| mux_tree_size30_8_out | Yes | Yes | Yes |
| mux_tree_size20_6_out | Yes | Yes | Yes |
| mux_tree_size20_7_out | Yes | Yes | Yes |
| mux_tree_size20_8_out | No | Yes | No |
| direct_interc_38_out | Yes | Yes | Yes |
| direct_interc_39_out | Yes | Yes | Yes |
| direct_interc_42_out | Yes | Yes | Yes |
| direct_interc_43_out | Yes | Yes | Yes |
| direct_interc_44_out | Yes | Yes | Yes |
| direct_interc_45_out | Yes | Yes | Yes |
| mux_tree_size4_2_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_2_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_9_out | Yes | Yes | Yes |
| mux_tree_size30_10_out | Yes | Yes | Yes |
| mux_tree_size30_11_out | Yes | Yes | Yes |
| mux_tree_size20_9_out | Yes | Yes | Yes |
| mux_tree_size20_10_out | Yes | Yes | Yes |
| mux_tree_size20_11_out | No | No | No |
| direct_interc_46_out | Yes | Yes | Yes |
| direct_interc_47_out | Yes | Yes | Yes |
| direct_interc_50_out | Yes | Yes | Yes |
| direct_interc_51_out | Yes | Yes | Yes |
| direct_interc_52_out | Yes | Yes | Yes |
| direct_interc_53_out | Yes | Yes | Yes |
| mux_tree_size4_3_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_3_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_12_out | Yes | Yes | Yes |
| mux_tree_size30_13_out | Yes | Yes | Yes |
| mux_tree_size30_14_out | Yes | Yes | Yes |
| mux_tree_size20_12_out | Yes | Yes | Yes |
| mux_tree_size20_13_out | Yes | Yes | Yes |
| mux_tree_size20_14_out | Yes | Yes | Yes |
| direct_interc_54_out | Yes | Yes | Yes |
| direct_interc_55_out | Yes | Yes | Yes |
| direct_interc_58_out | Yes | Yes | Yes |
| direct_interc_59_out | Yes | Yes | Yes |
| direct_interc_60_out | Yes | Yes | Yes |
| direct_interc_61_out | Yes | Yes | Yes |
| mux_tree_size4_4_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_4_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_15_out | Yes | Yes | Yes |
| mux_tree_size30_16_out | Yes | Yes | Yes |
| mux_tree_size30_17_out | Yes | Yes | Yes |
| mux_tree_size20_15_out | Yes | Yes | Yes |
| mux_tree_size20_16_out | Yes | Yes | Yes |
| mux_tree_size20_17_out | Yes | Yes | Yes |
| direct_interc_62_out | Yes | Yes | Yes |
| direct_interc_63_out | Yes | Yes | Yes |
| direct_interc_66_out | Yes | Yes | Yes |
| direct_interc_67_out | Yes | Yes | Yes |
| direct_interc_68_out | Yes | Yes | Yes |
| direct_interc_69_out | Yes | Yes | Yes |
| mux_tree_size4_5_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_5_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_18_out | Yes | Yes | Yes |
| mux_tree_size30_19_out | Yes | Yes | Yes |
| mux_tree_size30_20_out | Yes | Yes | Yes |
| mux_tree_size20_18_out | Yes | Yes | Yes |
| mux_tree_size20_19_out | Yes | Yes | Yes |
| mux_tree_size20_20_out | Yes | Yes | Yes |
| direct_interc_70_out | Yes | Yes | Yes |
| direct_interc_71_out | Yes | Yes | Yes |
| direct_interc_74_out | Yes | Yes | Yes |
| direct_interc_75_out | Yes | Yes | Yes |
| direct_interc_76_out | Yes | Yes | Yes |
| direct_interc_77_out | Yes | Yes | Yes |
| mux_tree_size4_6_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_6_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_21_out | Yes | Yes | Yes |
| mux_tree_size30_22_out | Yes | Yes | Yes |
| mux_tree_size30_23_out | Yes | Yes | Yes |
| mux_tree_size20_21_out | Yes | Yes | Yes |
| mux_tree_size20_22_out | Yes | Yes | Yes |
| mux_tree_size20_23_out | Yes | Yes | Yes |
| direct_interc_78_out | Yes | Yes | Yes |
| direct_interc_79_out | Yes | Yes | Yes |
| direct_interc_82_out | Yes | Yes | Yes |
| direct_interc_83_out | Yes | Yes | Yes |
| direct_interc_84_out | Yes | Yes | Yes |
| direct_interc_85_out | Yes | Yes | Yes |
| mux_tree_size4_7_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_7_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_24_out | Yes | Yes | Yes |
| mux_tree_size30_25_out | Yes | Yes | Yes |
| mux_tree_size30_26_out | Yes | Yes | Yes |
| mux_tree_size20_24_out | Yes | Yes | Yes |
| mux_tree_size20_25_out | Yes | Yes | Yes |
| mux_tree_size20_26_out | Yes | Yes | Yes |
| direct_interc_86_out | Yes | Yes | Yes |
| direct_interc_87_out | Yes | Yes | Yes |
| direct_interc_90_out | Yes | Yes | Yes |
| direct_interc_91_out | Yes | Yes | Yes |
| direct_interc_92_out | Yes | Yes | Yes |
| direct_interc_93_out | Yes | Yes | Yes |
| mux_tree_size4_8_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_8_fle_reg_out | Yes | Yes | Yes |
| mux_tree_size30_27_out | Yes | Yes | Yes |
| mux_tree_size30_28_out | Yes | Yes | Yes |
| mux_tree_size30_29_out | Yes | Yes | Yes |
| mux_tree_size20_27_out | Yes | Yes | Yes |
| mux_tree_size20_28_out | Yes | Yes | Yes |
| mux_tree_size20_29_out | Yes | Yes | Yes |
| direct_interc_94_out | Yes | Yes | Yes |
| direct_interc_95_out | Yes | Yes | Yes |
| direct_interc_98_out | Yes | Yes | Yes |
| direct_interc_99_out | Yes | Yes | Yes |
| direct_interc_100_out | Yes | Yes | Yes |
| direct_interc_101_out | Yes | Yes | Yes |
| mux_tree_size4_9_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_cout | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_sc_out | Yes | Yes | Yes |
| logical_tile_clb_mode_default__fle_9_fle_reg_out | Yes | Yes | Yes |
| direct_interc_24_out | Yes | Yes | Yes |
| direct_interc_25_out | Yes | Yes | Yes |
| direct_interc_32_out | Yes | Yes | Yes |
| direct_interc_33_out | Yes | Yes | Yes |
| direct_interc_40_out | Yes | Yes | Yes |
| direct_interc_41_out | Yes | Yes | Yes |
| direct_interc_48_out | Yes | Yes | Yes |
| direct_interc_49_out | Yes | Yes | Yes |
| direct_interc_56_out | Yes | Yes | Yes |
| direct_interc_57_out | Yes | Yes | Yes |
| direct_interc_64_out | Yes | Yes | Yes |
| direct_interc_65_out | Yes | Yes | Yes |
| direct_interc_72_out | Yes | Yes | Yes |
| direct_interc_73_out | Yes | Yes | Yes |
| direct_interc_80_out | Yes | Yes | Yes |
| direct_interc_81_out | Yes | Yes | Yes |
| direct_interc_88_out | Yes | Yes | Yes |
| direct_interc_89_out | Yes | Yes | Yes |
| direct_interc_96_out | Yes | Yes | Yes |
| direct_interc_97_out | Yes | Yes | Yes |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |